return i915_drm_resume(dev);
 }
 
+static void disable_engines_irq(struct drm_i915_private *dev_priv)
+{
+       struct intel_engine_cs *engine;
+
+       /* Ensure irq handler finishes, and not run again. */
+       disable_irq(dev_priv->drm.irq);
+       for_each_engine(engine, dev_priv)
+               tasklet_kill(&engine->irq_tasklet);
+}
+
+static void enable_engines_irq(struct drm_i915_private *dev_priv)
+{
+       enable_irq(dev_priv->drm.irq);
+}
+
 /**
  * i915_reset - reset chip after a hang
  * @dev: drm device to reset
        error->reset_count++;
 
        pr_notice("drm/i915: Resetting chip after gpu hang\n");
+
+       disable_engines_irq(dev_priv);
        ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
+       enable_engines_irq(dev_priv);
+
        if (ret) {
                if (ret != -ENODEV)
                        DRM_ERROR("Failed to reset chip: %i\n", ret);
 
        struct i915_gem_context *incomplete_ctx;
        bool ring_hung;
 
-       /* Ensure irq handler finishes, and not run again. */
-       tasklet_kill(&engine->irq_tasklet);
        if (engine->irq_seqno_barrier)
                engine->irq_seqno_barrier(engine);