dmaengine: dma-jz4780: Set DTCn register explicitly

Normally, we wouldn't set the channel transfer count register directly
when using descriptor-driven transfers. However, there is no harm in
doing so, and it allows jz4780_dma_desc_residue() to report the correct
residue of an ongoing transfer, no matter when it is called.

Signed-off-by: Daniel Silsby <dansilsby@gmail.com>
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c
index d055602a92ca3b5aa0e8f4b50840388d8e7e6a0e..d3b915ec8a09d266a2ba90000f3077d3f85fa689 100644 (file)
--- a/drivers/dma/dma-jz4780.c
+++ b/drivers/dma/dma-jz4780.c
@@ -532,6 +532,15 @@ static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan)
        jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT,
                              jzchan->transfer_type);
 
+       /*
+        * Set the transfer count. This is redundant for a descriptor-driven
+        * transfer. However, there can be a delay between the transfer start
+        * time and when DTCn reg contains the new transfer count. Setting
+        * it explicitly ensures residue is computed correctly at all times.
+        */
+       jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DTC,
+                               jzchan->desc->desc[jzchan->curr_hwdesc].dtc);
+
        /* Write descriptor address and initiate descriptor fetch. */
        desc_phys = jzchan->desc->desc_phys +
                    (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc));