}
 EXPORT_SYMBOL_GPL(clk_set_parent);
 
+static int clk_core_set_phase_nolock(struct clk_core *core, int degrees)
+{
+       int ret = -EINVAL;
+
+       lockdep_assert_held(&prepare_lock);
+
+       if (!core)
+               return 0;
+
+       trace_clk_set_phase(core, degrees);
+
+       if (core->ops->set_phase)
+               ret = core->ops->set_phase(core->hw, degrees);
+
+       trace_clk_set_phase_complete(core, degrees);
+
+       return ret;
+}
+
 /**
  * clk_set_phase - adjust the phase shift of a clock signal
  * @clk: clock signal source
  */
 int clk_set_phase(struct clk *clk, int degrees)
 {
-       int ret = -EINVAL;
+       int ret;
 
        if (!clk)
                return 0;
                degrees += 360;
 
        clk_prepare_lock();
-
-       trace_clk_set_phase(clk->core, degrees);
-
-       if (clk->core->ops->set_phase)
-               ret = clk->core->ops->set_phase(clk->core->hw, degrees);
-
-       trace_clk_set_phase_complete(clk->core, degrees);
-
-       if (!ret)
-               clk->core->phase = degrees;
-
+       ret = clk_core_set_phase_nolock(clk->core, degrees);
        clk_prepare_unlock();
 
        return ret;