Modifications for 1.1.6:
======================================================================
+* Patch by Erik Theisen, 29 Mar 2002:
+ - Eliminate redundant 405 I2C controller reset
+ - Fix "deprecated multi-line string" warning
+ - Reenable multi-EEPROM support for the W7OLMC target
+ - Adjust W7OLMC's StrataFlash chip select to work with
+ bigger and therefor slower devices
+
+* Moved OCM init into 4xx start.S and out of board/*
+ Patch by Andrew May, 28 Mar 2002
+
+* Add CONFIG_NET_MULTI support to all GT64260 boards
+ Patch by Rich Ireland, 28 Mar 2002
+
+* 74xx_7xx BAT manipulation patch
+ Patch by Rich Ireland, 27 Mar 2002
+
+* Fix header file problems
+ Patch by Pierre Aubert, , 25 Mar 2002
+
+* Galileo performance patches
+ Patches by Nye Liu, 26 Mar 2002
+
+* Add support for TQM8260 @ 300MHz
+
* Patch by Jim Thompson, 21 Mar 2002:
- misc. Sandpoint8245 / Musenki patches
# All boards can come with 50 MHz (default), 66MHz or 80MHz clock,
# but only 855 and 860 boards may come with FEC
# and 823 boards may have LCD support
-xtract = $(subst _L2,,$(subst _66MHz,,$(subst _80MHz,,$(subst _266MHz,,$(subst _LCD,,$(subst _FEC,,$(subst _config,,$1)))))))
+xtract = $(subst _L2,,$(subst _66MHz,,$(subst _80MHz,,$(subst _266MHz,,$(subst _300MHz,,$(subst _LCD,,$(subst _FEC,,$(subst _config,,$1))))))))
FPS850L_config \
TQM823L_config \
TQM8260_config \
TQM8260_L2_config \
TQM8260_266MHz_config \
+TQM8260_300MHz_config \
TQM8260_L2_266MHz_config: unconfig
@echo "Configuring for $(call xtract,$@) Board..." ; \
cd ./include ; \
echo "... with L2 Cache support (60x Bus Mode)" ; \
else \
echo "#undef CONFIG_L2_CACHE" >>include/config.h ; \
- echo "... without L2 Cache support (82xx Bus Mode)" ; \
+ echo "... without L2 Cache support" ; \
fi
@[ -z "$(findstring _266MHz,$@)" ] || \
{ echo "#define CONFIG_266MHz" >>include/config.h ; \
echo "... with 266MHz system clock" ; \
}
+ @[ -z "$(findstring _300MHz,$@)" ] || \
+ { echo "#define CONFIG_300MHz" >>include/config.h ; \
+ echo "... with 300MHz system clock" ; \
+ }
@echo "#include <config_$(call xtract,$@).h>" >>include/config.h
#########################################################################
#include "eth.h"
#include "eth_addrtbl.h"
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
+
+#define GT6426x_ETH_BUF_SIZE 1536
+
/* if you like verbose output, turn this on! */
#undef DEBUG
/*
* The GT doc's say that after Rst is deasserted, and the PHY
- * reports autoneg compleate, it runs through its autoneg
+ * reports autoneg complete, it runs through its autoneg
* procedures. This doesn't seem to be the case for MII
* PHY's. To work around this check for link up && autoneg
- * compleate when initilizing the port. If they are both set,
+ * complete when initilizing the port. If they are both set,
* then restart PHY autoneg. Of course, it may be something
- * compleatly different.
+ * completly different.
*/
#ifdef CONFIG_ETHER_PORT_MII
# define RESTART_AUTONEG
#endif
-/* do this if you want to filter for our mac */
-#define USE_MAC_HASH_TABLE
-
/* do this if you dont want to use snooping */
#define USE_SOFTWARE_CACHE_MANAGEMENT
#define FLUSH_AND_INVALIDATE_DCACHE(a,b)
#define INVALIDATE_DCACHE(a,b)
#endif
+struct eth_dev_s {
+ eth0_tx_desc_single *eth_tx_desc;
+ eth0_rx_desc_single *eth_rx_desc;
+ char *eth_tx_buffer;
+ char *eth_rx_buffer[NR];
+ int tdn, rdn;
+ int dev;
+ unsigned int reg_base;
+};
-/* locals */
-static eth0_tx_desc_single *eth0_tx_desc;
-static eth0_rx_desc_single *eth0_rx_desc;
-static char *eth0_tx_buffer;
-static char *eth0_rx_buffer[NR];
-
#ifdef ZUMA_NTL
/* for intel LXT972 */
static const char ether_port_phy_addr[3]={0,1,2};
static const char ether_port_phy_addr[3]={4,5,6};
#endif
-#define ETHER_PORT_PHY (ether_port_phy_addr[CONFIG_ETHER_PORT])
-
-/* calculate the offset to the desired ethernet registers */
-/* the registers are offset by 0x400 for each port -- see the headers */
-#define REG_OFF (CONFIG_ETHER_PORT * ETHERNET_PORTS_DIFFERENCE_OFFSETS)
static inline unsigned short
miiphy_read_ret(unsigned short phy, unsigned short reg)
RESET - Reset adapter
***************************************************************************/
void
-evb64260_eth0_reset(bd_t *bis)
+gt6426x_eth_reset(void *v)
{
+ /* we should do something here...
+ struct eth_device *wp = (struct eth_device *)v;
+ struct eth_dev_s *p = wp->priv;
+ */
+
printf ("RESET\n");
/* put the card in its initial state */
}
-static void evb64260_handle_SMI(unsigned int icr)
+static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
{
#ifdef DEBUG
printf("SMI interrupt: ");
if(icr&0x10000000) {
unsigned int psr;
- psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF);
+ psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
#ifdef DEBUG
printf("PHY state change:\n"
- " GT:%s:%s:%s:%s\n"
+ " GT:%s:%s:%s:%s\n",
psr&1?"100":" 10",
psr&8?" Link":"nLink",
psr&2?"FD":"HD",
#ifdef ZUMA_NTL /* non-standard mii reg (intel lxt972a) */
{
unsigned short mii_11;
- mii_11=miiphy_read_ret(ETHER_PORT_PHY,0x11);
+ mii_11=miiphy_read_ret(ether_port_phy_addr[p->dev],0x11);
printf(" mii:%s:%s:%s:%s %s:%s %s\n",
mii_11&(1<<14)?"100":" 10",
}
static int
-evb64260_eth0_receive(unsigned int icr)
+gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
{
int eth_len=0;
char *eth_data;
- eth0_rx_desc_single *rx=ð0_rx_desc[(RDN_ETH0)];
+ eth0_rx_desc_single *rx=&p->eth_rx_desc[(p->rdn)];
INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
eth_len = (unsigned int)
(rx->buff_size_byte_count) & 0x0000ffff;
- eth_data = (char *) eth0_rx_buffer[RDN_ETH0];
+ eth_data = (char *) p->eth_rx_buffer[p->rdn];
#ifdef DEBUG
if (eth_len) {
/* let the upper layer handle the packet */
NetReceive (eth_data, eth_len);
- rx->buff_size_byte_count = 1536<<16;
+ rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
/* GT96100 Owner */
FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
- RDN_ETH0 ++;
- if (RDN_ETH0 == NR) {RDN_ETH0 = 0;}
+ p->rdn ++;
+ if (p->rdn == NR) {p->rdn = 0;}
sync();
/* Start Rx*/
- GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x00000080);
+ GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080);
#ifdef DEBUG
{
POLL - look for an rx frame, handle other conditions
***************************************************************************/
int
-evb64260_eth0_poll(void)
+gt6426x_eth_poll(void *v)
{
- unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + REG_OFF);
+ struct eth_device *wp = (struct eth_device *)v;
+ struct eth_dev_s *p = wp->priv;
+ unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base);
if(icr) {
- GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER, 0);
+ GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0);
#ifdef DEBUG
printf("poll got ICR %08x\n", icr);
#endif
/* SMI done or PHY state change*/
- if(icr&0x30000000) evb64260_handle_SMI(icr);
+ if(icr&0x30000000) gt6426x_handle_SMI(p, icr);
}
/* always process. We aren't using RX interrupts */
- return evb64260_eth0_receive(icr);
+ return gt6426x_eth_receive(p, icr);
}
/**************************************************************************
TRANSMIT - Transmit a frame
***************************************************************************/
int
-evb64260_eth0_transmit(unsigned int s, volatile char *p)
+gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s)
{
+ struct eth_device *wp = (struct eth_device *)v;
+ struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv;
+#ifdef DEBUG
unsigned int old_command_stat,old_psr;
- eth0_tx_desc_single *tx=ð0_tx_desc[(TDN_ETH0)];
+#endif
+ eth0_tx_desc_single *tx=&dev->eth_tx_desc[dev->tdn];
/* wait for tx to be ready */
INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
while (tx->command_status & 0x80000000) {
int i;
for(i=0;i<1000;i++);
- INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
+ INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
}
-
- GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + REG_OFF,
+
+ GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base,
(unsigned int)tx);
#ifdef DEBUG
printf("copying to tx_buffer [%p], length %x, desc = %p\n",
- eth0_tx_buffer, s, eth0_tx_desc);
+ dev->eth_tx_buffer, s, dev->eth_tx_desc);
#endif
- memcpy(eth0_tx_buffer, (char *) p, s);
+ memcpy(dev->eth_tx_buffer, (char *) p, s);
- tx->buff_pointer = eth0_tx_buffer;
+ tx->buff_pointer = dev->eth_tx_buffer;
tx->bytecount_reserved = ((__u16)s) << 16;
/* 31 - own
* 22 - gencrc
* 18:16 - pad, last, first */
tx->command_status = (1<<31) | (1<<22) | (7<<16);
-#if 0
+#if 0
/* FEr #18 */
tx->next_desc = NULL;
#else
tx->next_desc =
(struct eth0_tx_desc_struct *)
- ð0_tx_desc[(TDN_ETH0+1)%NT].bytecount_reserved;
+ &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved;
/* cpu owned */
- eth0_tx_desc[(TDN_ETH0+1)%NT].command_status = (7<<16); /* pad, last, first */
+ dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16); /* pad, last, first */
#endif
+#ifdef DEBUG
old_command_stat=tx->command_status,
- old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF);
+ old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
+#endif
FLUSH_DCACHE((unsigned int)tx,
- (unsigned int)ð0_tx_desc[(TDN_ETH0+2)%NT]);
+ (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]);
- FLUSH_DCACHE((unsigned int)eth0_tx_buffer,(unsigned int)eth0_tx_buffer+s);
+ FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s);
- GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x01000000);
+ GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000);
#ifdef DEBUG
{
printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr);
/* wait for tx to be ready */
do {
- unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF);
+ unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
command_stat=tx->command_status;
if(command_stat!=old_command_stat || psr !=old_psr) {
printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr);
old_command_stat = command_stat;
old_psr = psr;
}
- // evb64260_eth0_poll();
+ /* gt6426x_eth0_poll(); */
} while (command_stat & 0x80000000);
-
+
printf("sent %d byte frame\n", s);
if((command_stat & (3<<15)) == 3) {
DISABLE - Turn off ethernet interface
***************************************************************************/
void
-evb64260_eth0_disable(void)
+gt6426x_eth_disable(void *v)
{
- GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x80008000);
+ struct eth_device *wp = (struct eth_device *)v;
+ struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
+
+ GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000);
}
/**************************************************************************
MII utilities - dump mii registers
***************************************************************************/
static void
-evb64260_dump_mii(bd_t *bis, unsigned short phy)
+gt6426x_dump_mii(bd_t *bis, unsigned short phy)
{
printf("mii reg 0 - 3: %04x %04x %04x %04x\n",
miiphy_read_ret(phy, 0x0),
* restart autoneg - something screwy with FD/HD
* unless we do this. */
static void
-check_phy_state(void)
+check_phy_state(struct eth_dev_s *p)
{
- int bmsr = miiphy_read_ret(ETHER_PORT_PHY, PHY_BMSR);
- int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF);
+ int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_BMSR);
+ int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
if ((psr & 1<<3) && (bmsr & PHY_BMSR_LS)) {
- int nego = miiphy_read_ret(ETHER_PORT_PHY, PHY_ANAR) &
- miiphy_read_ret(ETHER_PORT_PHY, PHY_ANLPAR);
+ int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANAR) &
+ miiphy_read_ret(ether_port_phy_addr[p->dev], PHY_ANLPAR);
int want;
if (nego & PHY_ANLPAR_TXFD) {
if ((psr & 0x3) != want) {
printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
psr & 0x3, want);
- miiphy_write(ETHER_PORT_PHY,0,
- miiphy_read_ret(ETHER_PORT_PHY,0) | (1<<9));
+ miiphy_write(ether_port_phy_addr[p->dev],0,
+ miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
udelay(10000); /* the EVB's GT takes a while to notice phy
went down and up */
}
PROBE - Look for an adapter, this routine's visible to the outside
***************************************************************************/
int
-evb64260_eth0_probe(bd_t *bis)
+gt6426x_eth_probe(void *v, bd_t *bis)
{
- static int initted=0;
-
+ struct eth_device *wp = (struct eth_device *)v;
+ struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
+ int dev = p->dev;
+ unsigned int reg_base = p->reg_base;
unsigned long temp;
int i;
- if(initted) {
- GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x00000080);
- return 0;
+ if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS ))
+ { /* This should never happen */
+ printf("%s: Invalid device %d\n", __FUNCTION__, dev );
+ return 0;
}
- initted=1;
-
#ifdef DEBUG
+ printf ("%s: initializing %s\n", __FUNCTION__, wp->name );
printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n",
GTREGREAD(COMM_UNIT_ARBITER_CONTROL),
GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER));
// clear MIB counters
for(i=0;i<255; i++)
- temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + REG_OFF +i);
+ temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i);
#ifdef ZUMA_NTL
/* for intel LXT972 */
led 2: 0xc=link/rxact
led 3: 0x2=rxact (N/C)
strch: 0,2=30 ms, enable */
- miiphy_write(ETHER_PORT_PHY, 20, 0x1c22);
+ miiphy_write(ether_port_phy_addr[p->dev], 20, 0x1c22);
/* 2.7ns port rise time */
- //miiphy_write(ETHER_PORT_PHY, 30, 0x0<<10);
-#else
+ /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
+#else
/* already set up in mpsc.c */
//GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38); /* b400 */
-
+
/* already set up in sdram_init.S... */
/* MPSC0, MPSC1, RMII */
//GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102); /* f010 */
* 9 - 1: RIFB - interrupt on frame boundaries only
* 6:7 - 00: big endian rx and tx
* 5:2 - 1111: 15 retries */
- GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + REG_OFF,
+ GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base,
(2<<12) | (1<<9) | (0xf<<2) ); /* 2440 */
#ifndef USE_SOFTWARE_CACHE_MANAGEMENT
/* enable rx/tx desc/buffer cache snoop */
- GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + CONFIG_ETHER_PORT*0x20,
+ GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
&temp); /* f200 */
temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30);
- GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + CONFIG_ETHER_PORT*0x20,
+ GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
temp);
#endif
* 1000 1101 0000 0000 [4d00]
* 20 - 0=MII 1=RMII
* 19 - 0=speed autoneg
- * 15:14 - framesize 1536
+ * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE)
* 11 - no force link pass
* 10 - 1=disable fctl autoneg
* 8 - override prio ?? */
temp = 0x00004d00;
#ifndef CONFIG_ETHER_PORT_MII
- temp |= (1<<20); // RMII
+ temp |= (1<<20); /* RMII */
#endif
/* set En */
- GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + REG_OFF,
+ GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base,
temp); /* 2408 */
/* hardcode E1 also? */
/* -- according to dox, this is safer due to extra pulldowns? */
- GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + 1 * 0x400,
+ if (dev<2) {
+ GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400,
temp); /* 2408 */
+ }
/* wake up MAC */ /* 2400 */
- GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + REG_OFF, &temp);
+ GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp);
temp |= (1<<7); /* enable port */
-#ifdef USE_MAC_HASH_TABLE
+#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
temp |= (1<<12); /* hash size 1/2k */
#else
temp |= 1; /* promisc */
#endif
- GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + REG_OFF, temp);
+ GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp);
/* 2400 */
#ifdef RESTART_AUTONEG
- check_phy_state();
+ check_phy_state(p);
#endif
printf("Waiting for link up..\n");
+ temp = 10000;
/* wait for link back up */
- while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + REG_OFF) & 8)){
+ while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8)
+ && (--temp > 0)){
udelay(10);
}
- printf("OK!\n");
-
- /* we're dealing with the first ethernet only for this stripped down
- * driver */
- TDN_ETH0=0;
- RDN_ETH0=0;
-
- eth0_tx_desc =
- (eth0_tx_desc_single *)
- (((unsigned int) malloc(sizeof (eth0_tx_desc_single) *
- (NT+1)) & 0xfffffff0) + 0x10);
- eth0_rx_desc =
- (eth0_rx_desc_single *)
- (((unsigned int) malloc(sizeof (eth0_rx_desc_single) *
- (NR+1)) & 0xfffffff0) + 0x10);
- eth0_tx_buffer =
- (char *) (((unsigned int) malloc(1536) & 0xfffffff0) + 0x10);
-
- for (temp = 0 ; temp < NR ; temp ++) {
- eth0_rx_buffer[temp] =
- (char *)
- (((unsigned int) malloc(1536) & 0xfffffff0) + 0x10);
+ if ( temp == 0) {
+ printf("Failed!\n");
+ return (0);
}
- eth0_tx_desc[(TDN_ETH0)].command_status = 0;
+ printf("OK!\n");
+
+ p->tdn = 0;
+ p->rdn = 0;
+ p->eth_tx_desc[p->tdn].command_status = 0;
- // Initialize Rx Side
+ /* Initialize Rx Side */
for (temp = 0; temp < NR; temp++) {
- eth0_rx_desc[temp].buff_pointer = eth0_rx_buffer[temp];
- eth0_rx_desc[temp].buff_size_byte_count = 1536<<16;
+ p->eth_rx_desc[temp].buff_pointer = p->eth_rx_buffer[temp];
+ p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
/* GT96100 Owner */
- eth0_rx_desc[temp].command_status = 0x80000000;
- eth0_rx_desc[temp].next_desc =
+ p->eth_rx_desc[temp].command_status = 0x80000000;
+ p->eth_rx_desc[temp].next_desc =
(struct eth0_rx_desc_struct *)
- ð0_rx_desc[(temp+1)%NR].buff_size_byte_count;
+ &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count;
}
- FLUSH_DCACHE((unsigned int)ð0_tx_desc[0],
- (unsigned int)ð0_tx_desc[NR]);
- FLUSH_DCACHE((unsigned int)ð0_rx_desc[0],
- (unsigned int)ð0_rx_desc[NR]);
-
- GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + REG_OFF,
- (unsigned int) eth0_tx_desc);
- GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + REG_OFF,
- (unsigned int) eth0_rx_desc);
- GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + REG_OFF,
- (unsigned int) eth0_rx_desc);
+ FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0],
+ (unsigned int)&p->eth_tx_desc[NR]);
+ FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0],
+ (unsigned int)&p->eth_rx_desc[NR]);
+
+ GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base,
+ (unsigned int) p->eth_tx_desc);
+ GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base,
+ (unsigned int) p->eth_rx_desc);
+ GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base,
+ (unsigned int) p->eth_rx_desc);
#ifdef DEBUG
printf ("\nRx descriptor pointer is %08x %08x\n",
- GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + REG_OFF),
- GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + REG_OFF));
+ GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base),
+ GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base));
printf ("\n\n%08x %08x\n",
- (unsigned int)eth0_rx_desc,eth0_rx_desc[0].command_status);
+ (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status);
printf ("Descriptor dump:\n");
- printf ("cmd status: %08x\n",eth0_rx_desc[0].command_status);
- printf ("byte_count: %08x\n",eth0_rx_desc[0].buff_size_byte_count);
- printf ("buff_ptr: %08x\n",(unsigned int)eth0_rx_desc[0].buff_pointer);
- printf ("next_desc: %08x\n\n",(unsigned int)eth0_rx_desc[0].next_desc);
- printf ("%08x\n",*(unsigned int *) ((unsigned int)eth0_rx_desc + 0x0));
- printf ("%08x\n",*(unsigned int *) ((unsigned int)eth0_rx_desc + 0x4));
- printf ("%08x\n",*(unsigned int *) ((unsigned int)eth0_rx_desc + 0x8));
+ printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status);
+ printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count);
+ printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer);
+ printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc);
+ printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0));
+ printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4));
+ printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8));
printf ("%08x\n\n",
- *(unsigned int *) ((unsigned int)eth0_rx_desc + 0xc));
+ *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc));
#endif
#ifdef DEBUG
- evb64260_dump_mii(bis,ETHER_PORT_PHY);
+ gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]);
#endif
-#ifdef USE_MAC_HASH_TABLE
+#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
{
- u8 *b=bis->bi_enetaddr;
- u32 macH= (b[0]<<8) | b[1];
- u32 macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5];
+ unsigned int hashtable_base;
+ u8 *b = (u8 *)(wp->enetaddr);
+ u32 macH, macL;
- /* mode 0, size 0x800 */
- unsigned int hashtable_base =initAddressTable(CONFIG_ETHER_PORT,0,1);
+ /* twist the MAC up into the way the discovery wants it */
+ macH= (b[0]<<8) | b[1];
+ macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5];
+ /* mode 0, size 0x800 */
+ hashtable_base =initAddressTable(dev,0,1);
+
if(!hashtable_base) {
- printf("initAddressTable failed\n");
- return -1;
+ printf("initAddressTable failed\n");
+ return 0;
}
- addAddressTableEntry(CONFIG_ETHER_PORT, macH, macL, 1, 0);
- GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + REG_OFF,
+ addAddressTableEntry(dev, macH, macL, 1, 0);
+ GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base,
hashtable_base);
}
#endif
/* Start Rx*/
- GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + REG_OFF, 0x00000080);
- return 0;
+ GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080);
+ printf("gt6426x eth device %d init success \n", dev );
+ return 1;
+}
+
+/* enter all the galileo ethernet devs into MULTI-BOOT */
+void
+gt6426x_eth_initialize(bd_t *bis)
+{
+ struct eth_device *dev;
+ struct eth_dev_s *p;
+ int devnum, x, temp;
+ char *s, *e, buf[64];
+
+#ifdef DEBUG
+ printf( "\n%s\n", __FUNCTION );
+#endif
+
+ for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) {
+ dev = calloc(sizeof(*dev), 1);
+ if (!dev) {
+ printf( "%s: gal_enet%d allocation failure, %s\n",
+ __FUNCTION__, devnum, "eth_device structure");
+ return;
+ }
+
+ /* must be less than NAMESIZE (16) */
+ sprintf(dev->name, "gal_enet%d", devnum);
+
+#ifdef DEBUG
+ printf( "Initializing %s\n", dev->name );
+#endif
+
+ /* Extract the MAC address from the environment */
+ switch (devnum)
+ {
+ case 0: s = "ethaddr"; break;
+#if (GAL_ETH_DEVS > 1)
+ case 1: s = "eth1addr"; break;
+#endif
+#if (GAL_ETH_DEVS > 2)
+ case 2: s = "eth2addr"; break;
+#endif
+ default: /* this should never happen */
+ printf( "%s: Invalid device number %d\n",
+ __FUNCTION__, devnum );
+ return;
+ }
+
+ temp = getenv_r (s, buf, sizeof(buf));
+ s = (temp > 0) ? buf : NULL;
+
+#ifdef DEBUG
+ printf ("Setting MAC %d to %s\n", devnum, s );
+#endif
+ for (x = 0; x < 6; ++x) {
+ dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e+1 : e;
+ }
+
+ dev->init = (void*)gt6426x_eth_probe;
+ dev->halt = (void*)gt6426x_eth_reset;
+ dev->send = (void*)gt6426x_eth_transmit;
+ dev->recv = (void*)gt6426x_eth_poll;
+
+ dev->priv = (void*)p = calloc( sizeof(*p), 1 );
+ if (!p)
+ {
+ printf( "%s: %s allocation failure, %s\n",
+ __FUNCTION__, dev->name, "Private Device Structure");
+ free(dev);
+ return;
+ }
+
+ p->dev = devnum;
+ p->tdn=0;
+ p->rdn=0;
+ p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS;
+
+ p->eth_tx_desc =
+ (eth0_tx_desc_single *)
+ (((unsigned int) malloc(sizeof (eth0_tx_desc_single) *
+ (NT+1)) & 0xfffffff0) + 0x10);
+ if (!p)
+ {
+ printf( "%s: %s allocation failure, %s\n",
+ __FUNCTION__, dev->name, "Tx Descriptor");
+ free(dev);
+ return;
+ }
+
+ p->eth_rx_desc =
+ (eth0_rx_desc_single *)
+ (((unsigned int) malloc(sizeof (eth0_rx_desc_single) *
+ (NR+1)) & 0xfffffff0) + 0x10);
+ if (!p->eth_rx_desc)
+ {
+ printf( "%s: %s allocation failure, %s\n",
+ __FUNCTION__, dev->name, "Rx Descriptor");
+ free(dev);
+ free(p);
+ return;
+ }
+
+ p->eth_tx_buffer =
+ (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
+ if (!p->eth_tx_buffer)
+ {
+ printf( "%s: %s allocation failure, %s\n",
+ __FUNCTION__, dev->name, "Tx Bufffer");
+ free(dev);
+ free(p);
+ free(p->eth_rx_desc);
+ return;
+ }
+
+ for (temp = 0 ; temp < NR ; temp ++) {
+ p->eth_rx_buffer[temp] =
+ (char *)
+ (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
+ if (!p->eth_rx_buffer[temp])
+ {
+ printf( "%s: %s allocation failure, %s\n",
+ __FUNCTION__, dev->name, "Rx Buffers");
+ free(dev);
+ free(p);
+ free(p->eth_tx_buffer);
+ free(p->eth_rx_desc);
+ free(p->eth_tx_desc);
+ while (temp >= 0)
+ free(p->eth_rx_buffer[--temp]);
+ return;
+ }
+ }
+
+
+ eth_register(dev);
+ }
}
+#endif /* CFG_CMD_NET && CONFIG_NET_MULTI */
* eth.h - header file for the polled mode GT ethernet driver
*/
-#ifndef __EVB64260_ETH_H__
-#define __EVB64260_ETH_H__
+#ifndef __GT6426x_ETH_H__
+#define __GT6426x_ETH_H__
#include <asm/types.h>
#include <asm/io.h>
#define NT 20 /* Number of Transmit buffers */
#define NR 20 /* Number of Receive buffers */
-#define EVB64260_ETH0_INT_THRE 20
-// #define CACHE_LINE_SIZE 0 // 32
#define MAX_BUFF_SIZE (1536+2*CACHE_LINE_SIZE) // 1600
#define ETHERNET_PORTS_DIFFERENCE_OFFSETS 0x400
extern char *eth0_rx_buffer[NR];
extern char *eth_data;
-int evb64260_eth0_poll(void);
-int evb64260_eth0_transmit(unsigned int s, volatile char *p);
-void evb64260_eth0_disable(void);
-int evb64260_eth0_probe(bd_t *bis);
-#endif
+extern int gt6426x_eth_poll(void *v);
+extern int gt6426x_eth_transmit(void *v, volatile char *p, unsigned int s);
+extern void gt6426x_eth_disable(void *v);
+extern int gt6426x_eth_probe(void *v, bd_t *bis);
+
+#endif /* __GT64260x_ETH_H__ */
#include "eth.h"
#include "eth_addrtbl.h"
-#define MAX_NUMBER_OF_ETHERNET_PORTS 3
#define TRUE 1
#define FALSE 0
#define PRINTF printf
-static u32 addressTableHashMode[ MAX_NUMBER_OF_ETHERNET_PORTS ];
-static u32 addressTableHashSize[ MAX_NUMBER_OF_ETHERNET_PORTS ];
-static addrTblEntry *addressTableBase[ MAX_NUMBER_OF_ETHERNET_PORTS ];
+#ifdef CONFIG_GT_USE_MAC_HASH_TABLE
-static const u32 hashLength[ MAX_NUMBER_OF_ETHERNET_PORTS ] = {
+static u32 addressTableHashMode[ GAL_ETH_DEVS ] = { 0, 0, 0 };
+static u32 addressTableHashSize[ GAL_ETH_DEVS ] = { 0, 0, 0 };
+static addrTblEntry *addressTableBase[ GAL_ETH_DEVS ] = { 0, 0, 0 };
+static void *realAddrTableBase[ GAL_ETH_DEVS ] = { 0, 0, 0 };
+
+static const u32 hashLength[ 2 ] = {
(0x8000), /* 8K * 4 entries */
(0x8000/16), /* 512 * 4 entries */
};
+/* Initialize the address table for a port, if needed */
unsigned int initAddressTable( u32 port, u32 hashMode, u32 hashSizeSelector)
{
unsigned int tableBase;
- int bytes=hashLength[hashSizeSelector] * sizeof(addrTblEntry);
- if(port<0 || port >= MAX_NUMBER_OF_ETHERNET_PORTS)
- return 0;
+ if( port < 0 || port >= GAL_ETH_DEVS ) {
+ printf("%s: Invalid port number %d\n", __FUNCTION__, port );
+ return 0;
+ }
+
+ if (hashMode > 1) {
+ printf("%s: Invalid Hash Mode %d\n", __FUNCTION__, port );
+ return 0;
+ }
+
+ if ( realAddrTableBase[port] &&
+ ( addressTableHashSize[port] != hashSizeSelector )) {
+ /* we have been here before,
+ * but now we want a different sized table
+ */
+ free( realAddrTableBase[port] );
+ realAddrTableBase[port] = 0;
+ addressTableBase[port] = 0;
- tableBase=(unsigned int) malloc(bytes+64);
+ }
- if(!tableBase) return 0;
+ tableBase = (unsigned int)addressTableBase[port];
+ /* we get called for every probe, so only do this once */
+ if ( !tableBase ) {
+ int bytes = hashLength[hashSizeSelector] * sizeof(addrTblEntry);
- // align to octal byte
- if(tableBase&63) tableBase=(tableBase+63) & ~63;
+ tableBase = (unsigned int)realAddrTableBase[port] = malloc(bytes+64);
- addressTableHashMode[port] = hashMode;
- addressTableHashSize[port] = hashSizeSelector;
- addressTableBase[port] = (addrTblEntry *)tableBase;
+ if(!tableBase)
+ {
+ printf("%s: alloc memory failed \n", __FUNCTION__);
+ return 0;
+ }
- memset((void *)tableBase,0,bytes);
+ /* align to octal byte */
+ if(tableBase&63) tableBase=(tableBase+63) & ~63;
+
+ addressTableHashMode[port] = hashMode;
+ addressTableHashSize[port] = hashSizeSelector;
+ addressTableBase[port] = (addrTblEntry *)tableBase;
+
+ memset((void *)tableBase,0,bytes);
+ }
return tableBase;
}
DCACHE_FLUSH_N_SYNC( (u32)entry, MAC_ENTRY_SIZE );
return( TRUE );
}
+
+#endif /* CONFIG_GT_USE_MAC_HASH_TABLE */
#include <galileo/gt64260R.h>
#include <net.h>
+#include <asm/io.h>
#include "eth.h"
#include "mpsc.h"
#include "i2c.h"
tmp |= CPU_CONF_AACK_DELAY;
tmp &= ~CPU_CONF_AACK_DELAY_2; /* New RGF */
+ /* Galileo claims this is necessary for all busses >= 100 MHz */
+ tmp |= CPU_CONF_FAST_CLK;
+
if (cpu == CPU_750CX) {
tmp &= ~CPU_CONF_DP_VALID; /* Safer, needed for CXe. RGF */
tmp &= ~CPU_CONF_AP_VALID;
- tmp &= ~CPU_CONF_FAST_CLK; /* Yeah. RGF */
} else {
tmp |= CPU_CONF_DP_VALID;
tmp |= CPU_CONF_AP_VALID;
/* this only works with the MPX bus */
tmp &= ~CPU_CONF_RD_OOO; /* Safer RGF */
- tmp &= ~CPU_CONF_PIPELINE; /* Safer RGF */
+ tmp |= CPU_CONF_PIPELINE;
tmp |= CPU_CONF_TA_DELAY;
GT_REG_WRITE(CPU_CONFIGURATION, tmp);
#ifdef CFG_L2
l2cache_enable();
#endif
+
#ifdef CONFIG_MPSC
mpsc_init2();
#endif
-#if 0
- /* disable the dcache and MMU */
- dcache_lock();
-// disable_addr_trans();
-// invalidate_bats();
-// dcache_disable();
-#endif
#ifdef ZUMA_NTL
zuma_mbox_init();
#endif
+
}
void
#endif /* ZUMA_NTL */
}
-#if (CONFIG_COMMANDS & CFG_CMD_NET)
-
-/*
- * ethernet handlers. mostly just pass off to routines in
- * eth.c
- */
-
-int
-eth_init(bd_t *bis)
-{
- return evb64260_eth0_probe(bis);
-}
-
-int
-eth_send(volatile void *packet, int length)
-{
-#ifdef DEBUG
- printf ("%s: %d byte packet @ 0x%p\n", __FUNCTION__, length, packet);
-#endif
- return evb64260_eth0_transmit(length, packet);
-}
-
-int
-eth_rx(void)
-{
- return evb64260_eth0_poll();
-}
-
-void
-eth_halt(void)
-{
- evb64260_eth0_disable();
-}
-
-#endif /* CFG_CMD_NET */
-
void
display_mem_map(void)
{
printf(" BOOT: base - 0x%08x\tsize - %dM bytes\twidth - %d bits\n",
base, size>>20, width);
}
+
sdram_init:
- /*-------------------------------------------------------------------
- * init OnChip Memory for a temporary stack
- *------------------------------------------------------------------- */
-
- lis r0, 0x7FFF
- ori r0, r0, 0xFFFF
- mfdcr r3, ocmiscntl /* get instr-side IRAM config */
- mfdcr r4, ocmdscntl /* get data-side IRAM config */
- and r3, r3, r0 /* disable data-side IRAM */
- and r4, r4, r0 /* disable data-side IRAM */
- mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
- mtdcr ocmdscntl, r4 /* set data-side IRAM config */
- isync
- lis r0, OCM_DATA_ADDR@h/* IRAM is mapped here */
- mtdcr ocmdsarc, r0 /* set data-side IRAM address */
- oris r4, r4, 0xC000 /* enable data-side IRAM */
- mtdcr ocmdscntl, r4 /* set data-side IRAM config */
- isync
-
- mfdcr r3, ocmdsarc /* set temp stackpointer (needed by CONS_Init) */
- andis. r3, r3, 0xFC00
- addi r1, r3, 0x1000-16
blr
sdram_init:
- /*-------------------------------------------------------------------
- * init OnChip Memory for a temporary stack
- *------------------------------------------------------------------- */
-
- lis r0, 0x7FFF
- ori r0, r0, 0xFFFF
- mfdcr r3, ocmiscntl /* get instr-side IRAM config */
- mfdcr r4, ocmdscntl /* get data-side IRAM config */
- and r3, r3, r0 /* disable data-side IRAM */
- and r4, r4, r0 /* disable data-side IRAM */
- mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
- mtdcr ocmdscntl, r4 /* set data-side IRAM config */
- isync
- lis r0, OCM_DATA_ADDR@h/* IRAM is mapped here */
- mtdcr ocmdsarc, r0 /* set data-side IRAM address */
- oris r4, r4, 0xC000 /* enable data-side IRAM */
- mtdcr ocmdscntl, r4 /* set data-side IRAM config */
- isync
-
- mfdcr r3, ocmdsarc /* set temp stackpointer (needed by CONS_Init) */
- andis. r3, r3, 0xFC00
- addi r1, r3, 0x1000-16
blr
int read_LM84_temp (int address)
{
unsigned char buffer[8];
- int rc;
+ /*int rc;*/
if (i2c_read (address, 0, 1, buffer, 1)) {
return (int) buffer[0];
ori r4, r4, CFG_W7O_EBC_PB0CR@l
mtdcr ebccfgd, r4
-#if defined(CFG_OCM_DATA_ADDR)
- /********************************************************************
- * Setup OCM - On Chip Memory, USED FOR INITIAL STACK.
- *******************************************************************/
- /* Setup OCM */
- addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */
- mtdcr ocmdsarc, r3
- addis r4, 0, 0xC000 /* OCM data area enabled */
- mtdcr ocmdscntl, r4
-#endif /* OCM setup */
-
/********************************************************************
* Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
*******************************************************************/
load_sernum_ethaddr(bd);
#endif
-#ifdef CONFIG_EVB64260
+#ifdef CFG_GT_6426x
/* handle the 2nd and 3rd ethernet addresses */
i = getenv_r ("eth1addr", tmp, sizeof(tmp));
#ifdef CONFIG_ETHADDR
"ethaddr=" MK_STR(CONFIG_ETHADDR) "\0"
#endif
+#ifdef CONFIG_ETH1ADDR
+ "eth1addr=" MK_STR(CONFIG_ETH1ADDR) "\0"
+#endif
#ifdef CONFIG_ETH2ADDR
"eth2addr=" MK_STR(CONFIG_ETH2ADDR) "\0"
#endif
-#ifdef CONFIG_ETH3ADDR
- "eth3addr=" MK_STR(CONFIG_ETH3ADDR) "\0"
-#endif
#ifdef CONFIG_IPADDR
"ipaddr=" MK_STR(CONFIG_IPADDR) "\0"
#endif
#ifdef CONFIG_ETHADDR
"ethaddr=" MK_STR(CONFIG_ETHADDR) "\0"
#endif
+#ifdef CONFIG_ETH1ADDR
+ "eth1addr=" MK_STR(CONFIG_ETH1ADDR) "\0"
+#endif
#ifdef CONFIG_ETH2ADDR
"eth2addr=" MK_STR(CONFIG_ETH2ADDR) "\0"
#endif
-#ifdef CONFIG_ETH3ADDR
- "eth3addr=" MK_STR(CONFIG_ETH3ADDR) "\0"
-#endif
#ifdef CONFIG_IPADDR
"ipaddr=" MK_STR(CONFIG_IPADDR) "\0"
#endif
/*
- *(C) Copyright 2001
+ * (C) Copyright 2001, 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
- * the License, or(at your option) any later version.
+ * the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
*/
#include <ppcboot.h>
+#ifdef CONFIG_MPC8260 /* only valid for MPC8260 */
#include <ioports.h>
+#endif
#include <i2c.h>
#if defined(CONFIG_SOFT_I2C)
-#undef DEBUG_I2C
+#define DEBUG_I2C
/*-----------------------------------------------------------------------
#ifdef DEBUG_I2C
-#define PRINTD(x) printf x
+#define PRINTD(fmt,args...) printf (fmt ,##args)
#else
-#define PRINTD(x)
+#define PRINTD(fmt,args...)
#endif
/*-----------------------------------------------------------------------
*/
static void send_reset(void)
{
+#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
+#endif
+#ifdef CONFIG_8xx
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+#endif
int j;
I2C_ACTIVE;
*/
static void send_start(void)
{
+#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
+#endif
+#ifdef CONFIG_8xx
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+#endif
I2C_DELAY;
I2C_SDA(1);
*/
static void send_stop(void)
{
+#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
+#endif
+#ifdef CONFIG_8xx
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+#endif
I2C_SCL(0);
I2C_DELAY;
*/
static void send_ack(int ack)
{
+#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
+#endif
+#ifdef CONFIG_8xx
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+#endif
I2C_ACTIVE;
I2C_SCL(0);
*/
static int write_byte(uchar data)
{
+#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
+#endif
+#ifdef CONFIG_8xx
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+#endif
int j;
int nack;
*/
static uchar read_byte(int ack)
{
+#ifdef CONFIG_MPC8260
volatile ioport_t *iop = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
+#endif
+#ifdef CONFIG_8xx
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+#endif
int data;
int j;
/*-----------------------------------------------------------------------
* Initialization
*/
-void i2c_init(int speed, int slaveaddr)
+void i2c_init (int speed, int slaveaddr)
{
- /*
- * WARNING: Do NOT save speed in a static variable: if the I2C routines are
- * called before RAM is initialized (to read the DIMM SPD, for instance),
- * RAM won't be usable and your system will crash.
- */
- send_reset();
+#ifdef CONFIG_8xx
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+#endif
+
+#ifdef I2C_INIT
+ I2C_INIT;
+#endif
+ /*
+ * WARNING: Do NOT save speed in a static variable: if the
+ * I2C routines are called before RAM is initialized (to read
+ * the DIMM SPD, for instance), RAM won't be usable and your
+ * system will crash.
+ */
+ send_reset ();
}
/*-----------------------------------------------------------------------
int i2c_probe(uchar addr)
{
send_start();
- if(write_byte((addr << 1) | 1)) /* read cycle */
- {
+ if(write_byte((addr << 1) | 1)) /* read cycle */ {
send_stop();
return(1);
}
if(alen > 0) {
if(write_byte(chip << 1)) { /* write cycle */
send_stop();
- PRINTD(("i2c_read, no chip responded %02X\n", chip));
+ PRINTD("i2c_read, no chip responded %02X\n", chip);
return(1);
}
while(alen-- > 0) {
send_start();
if(write_byte(chip << 1)) { /* write cycle */
send_stop();
- PRINTD(("i2c_write, no chip responded %02X\n", chip));
+ PRINTD("i2c_write, no chip responded %02X\n", chip);
return(1);
}
while(alen-- > 0) {
#endif /* CONFIG_SOFT_I2C */
-
{
int i, status;
- /* first clear out status registers */
+ /* Reset status register */
+ /* write 1 in SCMP and IRQA to clear these fields */
out8 (IIC_STS, 0x0A);
+
+ /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
out8 (IIC_EXTSTS, 0x8F);
__asm__ volatile ("eieio");
unsigned long freqOPB;
int val, divisor;
- /* Reset status register */
- /* write 1 in SCMP and IRQA to clear these fields */
- out8 (IIC_STS, 0x0A);
-
- /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
- out8 (IIC_EXTSTS, 0x8F);
-
/* Handle possible failed I2C state */
_i2c_bus_reset ();
bl ext_bus_cntlr_init
#endif
+#if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
+ /********************************************************************
+ * Setup OCM - On Chip Memory
+ *******************************************************************/
+ /* Setup OCM */
+ lis r0, 0x7FFF
+ ori r0, r0, 0xFFFF
+ mfdcr r3, ocmiscntl /* get instr-side IRAM config */
+ mfdcr r4, ocmdscntl /* get data-side IRAM config */
+ and r3, r3, r0 /* disable data-side IRAM */
+ and r4, r4, r0 /* disable data-side IRAM */
+ mtdcr ocmiscntl, r3 /* set instr-side IRAM config */
+ mtdcr ocmdscntl, r4 /* set data-side IRAM config */
+ isync
+
+ addis r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */
+ mtdcr ocmdsarc, r3
+ addis r4, 0, 0xC000 /* OCM data area enabled */
+ mtdcr ocmdscntl, r4
+ isync
+#endif
+
/*----------------------------------------------------------------------- */
/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
/*----------------------------------------------------------------------- */
#ifdef CONFIG_DTT_DS1621
#if !defined(CFG_EEPROM_PAGE_WRITE_ENABLE) || \
(CFG_EEPROM_PAGE_WRITE_BITS < 1)
-# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_
-BITS must be greater than 1 to use CONFIG_DTT_DS1621"
+# error "CFG_EEPROM_PAGE_WRITE_ENABLE must be defined and CFG_EEPROM_PAGE_WRITE_BITS must be greater than 1 to use CONFIG_DTT_DS1621"
#endif
#include <i2c.h>
#include <dtt.h>
extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
extern void _tlbia(void); /* invalidate all TLB entries */
+typedef enum {
+ IBAT0 = 0, IBAT1, IBAT2, IBAT3,
+ DBAT0, DBAT1, DBAT2, DBAT3
+} ppc_bat_t;
+
+extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
+extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
+
#endif /* __ASSEMBLY__ */
/* Block size masks */
#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
-/* On Chip Memory location */
-#define OCM_DATA_ADDR 0xF8000000
-
/* Configuration Port location */
#define CONFIG_PORT_ADDR 0xF0000500
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-/* On Chip Memory location */
-#define OCM_DATA_ADDR 0xF8000000
-
/* Configuration Port location */
#define CONFIG_PORT_ADDR 0xF0000500
#define CFG_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
-/* On Chip Memory location */
-#define OCM_DATA_ADDR 0xF8000000
-
/* Configuration Port location */
#define CONFIG_PORT_ADDR 0xF0000500
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-/* On Chip Memory location */
-#define OCM_DATA_ADDR 0xF8000000
-
/* Configuration Port location */
#define CONFIG_PORT_ADDR 0xF0000500
#define CFG_EBC_PB7CR DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
-/* On Chip Memory location */
-#define OCM_DATA_ADDR 0xF8000000
-
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
*/
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-/* On Chip Memory location */
-/* #define OCM_DATA_ADDR 0xF8000000 */
-
/* Configuration Port location */
/* #define CONFIG_PORT_ADDR 0xF0000500 */
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#endif
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
+#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
+#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
*/
#define CONFIG_EVB64260 1 /* this is an EVB64260 board */
+#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */
#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
#define CONFIG_MPSC
#define CONFIG_MPSC_PORT 0
-/* to change the default ethernet port, use this define (options: 0, 1, 2) */
-#define CONFIG_ETHER_PORT 0
+#define CONFIG_NET_MULTI /* attempt all available adapters */
+
+/* define this if you want to enable GT MAC filtering */
+#define CONFIG_GT_USE_MAC_HASH_TABLE
#undef CONFIG_ETHER_PORT_MII /* use RMII */
#define CFG_RESET_ADDRESS 0xfff00100
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
-#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */
+#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
/* areas to map different things with the GT in physical space */
#define CFG_DRAM_BANKS 4
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
+#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
+#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CONFIG_IP860 1 /* ...on a IP860 board */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#define CONFIG_BAUDRATE 19200
-#if 0
-#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
-#else
+#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#endif
#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \
+"\0load=tftp \"/tftpboot/ppcboot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 $(filesize)\0"
+
+#define CONFIG_ETHADDR 00:30:bf:01:02:d2
+#define CONFIG_IPADDR 10.0.0.5
+#define CONFIG_SERVERIP 10.0.0.2
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
/*
* Software (bit-bang) I2C driver configuration
*/
-#define I2C_PORT 1 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00000010)
-#define I2C_TRISTATE (iop->pdir &= ~0x00000010)
-#define I2C_READ ((iop->pdat & 0x00000010) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000010; \
- else iop->pdat &= ~0x00000010
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000020; \
- else iop->pdat &= ~0x00000020
+#define PB_SCL 0x00000020 /* PB 26 */
+#define PB_SDA 0x00000010 /* PB 27 */
+
+#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
+#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
+#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
#undef CFG_ENV_IS_IN_FLASH
#undef CFG_ENV_IS_IN_NVRAM
-#define CFG_ENV_IS_IN_EEPROM 1
+#define CFG_ENV_IS_IN_NVRAM
+//#define CFG_ENV_IS_IN_EEPROM 1
+#ifdef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_ADDR 0x20000000 /* use SRAM */
+#define CFG_ENV_SIZE (16<<10) /* use 16 kB */
+#endif /* CFG_ENV_IS_IN_NVRAM */
+
+#ifdef CFG_ENV_IS_IN_EEPROM
#define CFG_ENV_OFFSET 0 /* Start right at beginning of NVRAM */
#define CFG_ENV_SIZE 1024 /* Use only a part of it - it's slow! */
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
#define CFG_ENV_EEPROM_ADDR 0xA0
#define CFG_ENV_EEPROM_ADDR_LEN 2
#define CFG_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */
#define CFG_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
#define SRAM_SIZE (1 + (~(CFG_OR3 & BR_BA_MSK)))
+#define CFG_OR3_PRELIM CFG_OR3 /* Make sure to map early */
+#define CFG_BR3_PRELIM CFG_BR3 /* in case it's used for ENV */
/*
* BR4/OR4 - Board Control & Status (8 bit)
/*
* Miscellaneous configurable options
*/
-// #define CFG_LONGHELP /* undef to save memory */
+/* #define CFG_LONGHELP /X* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
-/* On Chip Memory location */
-#define OCM_DATA_ADDR 0xF8000000
-
#define CFG_ETHERNET_MAC_ADDR 0x00000000 /* Pass Ethernet MAC to VxWorks */
/*-----------------------------------------------------------------------
#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
-/* On Chip Memory location */
-#define OCM_DATA_ADDR 0xF8000000
-
#define CFG_ETHERNET_MAC_ADDR 0x00000000 /* Pass Ethernet MAC to VxWorks */
/*-----------------------------------------------------------------------
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in On Chip SRAM)
*/
-#define CFG_INIT_RAM_ADDR OCM_DATA_ADDR /* inside of On Chip SRAM */
-#define CFG_INIT_RAM_END 0x1000 /* End of On Chip SRAM */
-#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_RAM_ADDR OCM_DATA_ADDR /* inside of On Chip SRAM */
+#define CFG_INIT_RAM_END 0x1000 /* End of On Chip SRAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
+#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
+#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
* Imported from global configuration:
* CONFIG_L2_CACHE
* CONFIG_266MHz
+ * CONFIG_300MHz
*/
/*
# undef CONFIG_BUSMODE_60x /* bus mode: 8260 */
#endif
+/* The board with 300MHz CPU doesn't have L2 cache, but works in 60x bus mode */
+#ifdef CONFIG_300MHz
+# define CONFIG_BUSMODE_60x
+#endif
+
#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
+#ifndef CONFIG_300MHz
#define CONFIG_8260_CLKIN 66666666 /* in Hz */
+#else
+#define CONFIG_8260_CLKIN 83333000 /* in Hz */
+#endif
#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
#define CONFIG_BAUDRATE 230400
* defines for the various registers affected by the HRCW e.g. changing
* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
*/
-#ifndef CONFIG_266MHz
-#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
+#if defined(CONFIG_266MHz)
+#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
+ HRCW_MODCK_H0111)
+#elif defined(CONFIG_300MHz)
+#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | \
+ HRCW_MODCK_H0110)
#else
-#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
+#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
#endif
/* no slaves so just fill with zeros */
#define CFG_W7O_EBC_PB0CR 0xFFE38000
/* bank 1 is main flash */
-/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
-#define CFG_EBC_PB1AP 0x04850240
+/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
+#define CFG_EBC_PB1AP 0x05850240
/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
#define CFG_EBC_PB1CR 0xF00FC000
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
/* last 4 bits of the address */
+#define CFG_I2C_MULTI_EEPROMS
/*-----------------------------------------------------------------------
* Cache Configuration
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-/* On Chip Memory location */
-#define OCM_DATA_ADDR 0xF8000000
-
/* Configuration Port location */
#define CONFIG_PORT_ADDR 0xF0000500
#define CONFIG_EVB64260 1 /* this is an EVB64260 board */
#define ZUMA_NTL 1 /* temporary, will rename to something nicer */
+#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */
#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
#define CONFIG_MPSC_PORT 0
-/* to change the default ethernet port, use this define (options: 0, 1, 2) */
-#define CONFIG_ETHER_PORT 0
+#define CONFIG_NET_MULTI /* attempt all available adapters */
+/* define this if you want to enable GT MAC filtering */
+#define CONFIG_GT_USE_MAC_HASH_TABLE
+
#define CONFIG_ETHER_PORT_MII /* use MII */
#if 1
extern unsigned int INTERNAL_REG_BASE_ADDR;
+/*
+ * GT-6426x variants
+ */
+#define GT_64260 0 /* includes both 64260A and 64260B */
+#define GT_64261 1
+
+#if (CFG_GT_6426x == GT_64260)
+#define GAL_ETH_DEVS 3
+#elif (CFG_GT_6426x == GT_64261)
+#define GAL_ETH_DEVS 2
+#else
+#define GAL_ETH_DEVS 3 /* default to a 64260 */
+#endif
+
/****************************************/
/* GENERAL Definitions */
/****************************************/
PCI_DEVICE * pciFindDevice(unsigned short ven, unsigned short dev);
+#ifndef TRUE
+#define TRUE 1
+#endif
+#define PCI_CFG_BASE_ADDRESS_0 0x10
+#define PCI_MEMBASE_MASK ~0xf /* mask for memory base address */
+#define PCI_CFG_COMMAND 0x04
+#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */
+#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */
+#define PCI_CFG_LATENCY_TIMER 0x0d
+#define PCI_LATENCY_TIMER 0x20
+
#endif /* __INCpcih */
#define NULL ((void *)0)
#endif
+#ifndef _SIZE_T
+#include <linux/types.h>
+#endif
+
#undef offsetof
#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
#endif /*Void_t*/
#if __STD_C
-#include <stddef.h> /* for size_t */
+#include <linux/stddef.h> /* for size_t */
#else
#include <sys/types.h>
#endif /* __STD_C */
extern int eth_initialize(bd_t *bis); /* Initialize network subsystem */
extern int eth_register(struct eth_device* dev);/* Register network device */
extern void eth_try_another(void); /* Change the device */
+extern char *eth_get_enetaddr(void); /* get the current device MAC */
#endif
extern int eth_init(bd_t *bis); /* Initialize the device */
#if defined(CONFIG_HYMOD)
hymod_conf_t bi_hymod_conf; /* hymod configuration information */
#endif
-#if defined(CONFIG_EVB64260)
- /* the board has three onboard ethernet ports */
+#if defined(CFG_GT_6426x)
+ /* the board has two or three onboard ethernet ports */
unsigned char bi_enet1addr[6];
unsigned char bi_enet2addr[6];
#endif
#include <command.h>
#include "net.h"
+#ifdef CFG_GT_6426x
+extern int gt6426x_eth_initialize(bd_t *bis);
+#endif
+
#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
extern int eepro100_initialize(bd_t*);
static struct eth_device *eth_devices, *eth_current;
+char *eth_get_enetaddr(void)
+{
+ return eth_current->enetaddr;
+}
+
int eth_register(struct eth_device* dev)
{
struct eth_device *d;
#ifdef CONFIG_TULIP
dc21x4x_initialize(bis);
#endif
+#ifdef CFG_GT_6426x
+ gt6426x_eth_initialize(bis);
+#endif
if (!eth_devices)
printf("No ethernet found.\n");
eth_init(bis);
restart:
+#ifdef CONFIG_NET_MULTI
+ NetCopyEther(NetOurEther, eth_get_enetaddr());
+#else
NetCopyEther(NetOurEther, bis->bi_enetaddr);
+#endif
NetState = NETLOOP_CONTINUE;
LIB = lib$(ARCH).a
AOBJS = ppcstring.o ticks.o
-COBJS = cache.o ctype.o vsprintf.o extable.o string.o time.o \
- display_options.o zlib.o crc32.o kgdb.o ldiv.o
+
+COBJS = bat_rw.o cache.o crc32.o ctype.o display_options.o \
+ extable.o kgdb.o ldiv.o string.o time.o vsprintf.o zlib.o
+
OBJS = $(AOBJS) $(COBJS)
$(LIB): .depend $(OBJS)
--- /dev/null
+/*
+ * (C) Copyright 2002
+ * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <ppcboot.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+
+int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
+{
+ switch (bat) {
+ case IBAT0:
+ mtspr (IBAT0L, lower);
+ mtspr (IBAT0U, upper);
+ break;
+
+ case IBAT1:
+ mtspr (IBAT1L, lower);
+ mtspr (IBAT1U, upper);
+ break;
+
+ case IBAT2:
+ mtspr (IBAT2L, lower);
+ mtspr (IBAT2U, upper);
+ break;
+
+ case IBAT3:
+ mtspr (IBAT3L, lower);
+ mtspr (IBAT3U, upper);
+ break;
+
+ case DBAT0:
+ mtspr (DBAT0L, lower);
+ mtspr (DBAT0U, upper);
+ break;
+
+ case DBAT1:
+ mtspr (DBAT1L, lower);
+ mtspr (DBAT1U, upper);
+ break;
+
+ case DBAT2:
+ mtspr (DBAT2L, lower);
+ mtspr (DBAT2U, upper);
+ break;
+
+ case DBAT3:
+ mtspr (DBAT3L, lower);
+ mtspr (DBAT3U, upper);
+ break;
+
+ default:
+ return (-1);
+ }
+
+ return (0);
+}
+
+int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower)
+{
+ unsigned long register u;
+ unsigned long register l;
+
+ switch (bat) {
+ case IBAT0:
+ l = mfspr (IBAT0L);
+ u = mfspr (IBAT0U);
+ break;
+
+ case IBAT1:
+ l = mfspr (IBAT1L);
+ u = mfspr (IBAT1U);
+ break;
+
+ case IBAT2:
+ l = mfspr (IBAT2L);
+ u = mfspr (IBAT2U);
+ break;
+
+ case IBAT3:
+ l = mfspr (IBAT3L);
+ u = mfspr (IBAT3U);
+ break;
+
+ case DBAT0:
+ l = mfspr (DBAT0L);
+ u = mfspr (DBAT0U);
+ break;
+
+ case DBAT1:
+ l = mfspr (DBAT1L);
+ u = mfspr (DBAT1U);
+ break;
+
+ case DBAT2:
+ l = mfspr (DBAT2L);
+ u = mfspr (DBAT2U);
+ break;
+
+ case DBAT3:
+ l = mfspr (DBAT3L);
+ u = mfspr (DBAT3U);
+ break;
+
+ default:
+ return (-1);
+ }
+
+ *upper = u;
+ *lower = l;
+
+ return (0);
+}
projects / users / rw / ppcboot.git / commitdiff