Create a new profile for SFs in order to disable the command cache.
Each function command cache consumes ~500KB of memory, when using a
large number of SFs this savings is notable on memory constarined
systems.
Use a new profile to provide for future differences between SFs and PFs.
The mr_cache not used for non-PF functions, so it is excluded from the
new profile.
Signed-off-by: Parav Pandit <parav@mellanox.com>
Reviewed-by: Bodong Wang <bodong@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
        if (in_size <= 16)
                goto cache_miss;
 
-       for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
+       for (i = 0; i < dev->profile.num_cmd_caches; i++) {
                ch = &cmd->cache[i];
                if (in_size > ch->max_inbox_size)
                        continue;
        struct mlx5_cmd_msg *n;
        int i;
 
-       for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
+       for (i = 0; i < dev->profile.num_cmd_caches; i++) {
                ch = &dev->cmd.cache[i];
                list_for_each_entry_safe(msg, n, &ch->head, list) {
                        list_del(&msg->list);
        int k;
 
        /* Initialize and fill the caches with initial entries */
-       for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
+       for (k = 0; k < dev->profile.num_cmd_caches; k++) {
                ch = &cmd->cache[k];
                spin_lock_init(&ch->lock);
                INIT_LIST_HEAD(&ch->head);
 
 static struct mlx5_profile profile[] = {
        [0] = {
                .mask           = 0,
+               .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
        },
        [1] = {
                .mask           = MLX5_PROF_MASK_QP_SIZE,
                .log_max_qp     = 12,
+               .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
+
        },
        [2] = {
                .mask           = MLX5_PROF_MASK_QP_SIZE |
                                  MLX5_PROF_MASK_MR_CACHE,
                .log_max_qp     = LOG_MAX_SUPPORTED_QPS,
+               .num_cmd_caches = MLX5_NUM_COMMAND_CACHES,
                .mr_cache[0]    = {
                        .size   = 500,
                        .limit  = 250
                        .limit  = 4
                },
        },
+       [3] = {
+               .mask           = MLX5_PROF_MASK_QP_SIZE,
+               .log_max_qp     = LOG_MAX_SUPPORTED_QPS,
+               .num_cmd_caches = 0,
+       },
 };
 
 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
 
 };
 
 #define MLX5_DEFAULT_PROF       2
+#define MLX5_SF_PROF           3
 
 static inline int mlx5_flexible_inlen(struct mlx5_core_dev *dev, size_t fixed,
                                      size_t item_size, size_t num_items,
 
        mdev->priv.adev_idx = adev->id;
        sf_dev->mdev = mdev;
 
-       err = mlx5_mdev_init(mdev, MLX5_DEFAULT_PROF);
+       err = mlx5_mdev_init(mdev, MLX5_SF_PROF);
        if (err) {
                mlx5_core_warn(mdev, "mlx5_mdev_init on err=%d\n", err);
                goto mdev_err;
 
 struct mlx5_profile {
        u64     mask;
        u8      log_max_qp;
+       u8      num_cmd_caches;
        struct {
                int     size;
                int     limit;