(and it uses default address).
======================================================================
-Modifications since 0.6.4:
+Modifications for 0.7.0:
======================================================================
+* Directory reorganization: mode all CPU specific directories under
+ cpu/ , and all board specific directories under board/
+
+* Major re-write of the environment code; it now allows to place the
+ environment in NVRAM, EEPROM, or in full or partial sectors in
+ flash.
+
+* Added configuration for IP860 systems (MicroSys)
+
+* Added configuration for HERMES-PRO systems (Multidata)
+
* Fixes for ethernet on MPC8260 FEC
* Fixes for console on SCCx
#!/bin/sh
-[ -d LOG ] || mkdir LOG
+[ -d LOG ] || mkdir LOG || exit 1
-set -x
+LIST=" \
+ TQM823L TQM850L TQM855L TQM860L FPS850L SM850 \
+ ETX094 SPD823TS IVMS8 \
+ FADS823 FADS850SAR FADS860T MBX \
+ CPCI405 ADCIOP \
+ cogent_mpc8xx \
+ GENIETV \
+ cogent_mpc8260 hymod \
+ Sandpoint8240 \
+ hermes IP860 \
+"
-for i in TQM823L TQM850L TQM855L TQM860L FPS850L SM850 \
- ETX094 SPD823TS IVMS8 \
- FADS823 FADS850SAR FADS860T MBX \
- CPCI405 ADCIOP \
- cogent_mpc8xx \
- GENIETV \
- cogent_mpc8260 hymod \
- Sandpoint8240
+[ $# = 0 ] && set $LIST
+
+for target in $@
do
make distclean >/dev/null
- make ${i}_config
- make all 2>&1 >LOG/$i.MAKELOG | tee LOG/$i.ERR
- powerpc-linux-size ppcboot | tee -a LOG/$i.MAKELOG
+ make ${target}_config
+ make all 2>&1 >LOG/$target.MAKELOG | tee LOG/$target.ERR
+ powerpc-linux-size ppcboot | tee -a LOG/$target.MAKELOG
done
# load other configuration
include $(TOPDIR)/config.mk
-SUBDIRS = $(ARCH) $(CPU) $(BOARD) common net disk examples tools
+SUBDIRS = $(ARCH) cpu/$(CPU) board/$(BOARD) common net disk examples tools
#########################################################################
# ppcboot objects....order is important (i.e. start must be first)
-OBJS = $(CPU)/start.o \
+OBJS = cpu/$(CPU)/start.o \
common/libcommon.a
OBJS += net/libnet.a disk/libdisk.a
-OBJS += $(BOARD)/lib$(BOARD).a \
- $(CPU)/lib$(CPU).a \
+OBJS += board/$(BOARD)/lib$(BOARD).a \
+ cpu/$(CPU)/lib$(CPU).a \
$(ARCH)/lib$(ARCH).a
ifeq ($(CPU),ppc4xx)
-OBJS += $(CPU)/resetvec.o
+OBJS += cpu/$(CPU)/resetvec.o
endif
#########################################################################
echo "CPU = mpc8xx" >>config.mk ; \
echo "#include <config_$(@:_config=).h>" >config.h
+hermes_config : unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = hermes" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
+IP860_config : unconfig
+ @echo "Configuring for $(@:_config=) Board..." ; \
+ cd include ; \
+ echo "ARCH = ppc" > config.mk ; \
+ echo "BOARD = ip860" >>config.mk ; \
+ echo "CPU = mpc8xx" >>config.mk ; \
+ echo "#include <config_$(@:_config=).h>" >config.h
+
FADS823_config \
FADS850SAR_config \
FADS860T_config: unconfig
Directory Hierarchy:
====================
+- board Board dependend files
- common Misc architecture independend functions
+- cpu CPU specificfiles
- doc Documentation (don't expect too much)
- examples Example code for standalone applications, etc.
- include Header Files
- ppc Files generic to PowerPC architecture
- tools Tools to build S-Record or PPCBoot images, etc.
-- mpc8xx Files specific to Motorola MPC8xx CPUs
-- mpc8240 Files specific to Motorola MPC8240 CPU
-- mpc8260 Files specific to Motorola MPC8260 CPU
-- ppc4xx Files specific to IBM 4xx CPUs
+- cpu/mpc8xx Files specific to Motorola MPC8xx CPUs
+- cpu/mpc8240 Files specific to Motorola MPC8240 CPU
+- cpu/mpc8260 Files specific to Motorola MPC8260 CPU
+- cpu/ppc4xx Files specific to IBM 4xx CPUs
-- adciop Files specific to ADCIOP boards
-- cogent Files specific to Cogent boards
+- board/adciop Files specific to ADCIOP boards
+- board/cogent Files specific to Cogent boards
(need further configuration)
-- cpci405 Files specific to CPCI405 boards
-- etx094 Files specific to ETX_094 boards
-- fads Files specific to FADS boards
-- genietv Files specific to GENIETV boards
-- hymod Files specific to HYMOD boards
-- ivms8 Files specific to IVMS8 boards
-- mbx8xx Files specific to MBX boards
-- spd8xx Files specific to SPD8xxTS boards
-- sandpoint Files specific to Sandpoint boards
-- tqm8xx Files specific to TQM8xxL boards
+- board/cpci405 Files specific to CPCI405 boards
+- board/etx094 Files specific to ETX_094 boards
+- board/fads Files specific to FADS boards
+- board/genietv Files specific to GENIETV boards
+- board/hermes Files specific to HERMES boards
+- board/hymod Files specific to HYMOD boards
+- board/ip860 Files specific to IP860 boards
+- board/ivms8 Files specific to IVMS8 boards
+- board/mbx8xx Files specific to MBX boards
+- board/spd8xx Files specific to SPD8xxTS boards
+- board/sandpoint
+ Files specific to Sandpoint boards
+- board/tqm8xx Files specific to TQM8xxL boards
Software Configuration:
The following options need to be configured:
- CPU Type: Define exactly one of
- CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860
+ CONFIG_MPC823, CONFIG_MPC850, CONFIG_MPC855, CONFIG_MPC860
+ or CONFIG_MPC8240, CONFIG_MPC8260
or CONFIG_IOP480
or CONFIG_PPC405GP
- or CONFIG_MPC8260
- Board Type: Define exactly one of
- CONFIG_TQM823L, CONFIG_TQM850L, CONFIG_TQM855L,
- CONFIG_TQM860L, CONFIG_ETX094, CONFIG_ADCIOP,
- CONFIG_CPCI405, CONFIG_COGENT, CONFIG_FADS,
- CONFIG_SPD823TS,CONFIG_FPS850L, CONFIG_MBX,
- CONFIG_SM850
+ CONFIG_ADCIOP, CONFIG_COGENT, CONFIG_CPCI405, CONFIG_ETX094,
+ CONFIG_FADS, CONFIG_FPS850L, CONFIG_HERMES, CONFIG_IP860,
+ CONFIG_IVMS8, CONFIG_MBX, CONFIG_SM850, CONFIG_SPD823TS,
+ CONFIG_TQM823L, CONFIG_TQM850L, CONFIG_TQM855L, CONFIG_TQM860L
--- FIXME --- not tested yet:
CONFIG_TQM860, CONFIG_ADS,
CONFIG_RPXLITE, CONFIG_RPXCLASSIC, CONFIG_BSEIP,
- CFG_FLASH_WRITE_TOUT:
Timeout for Flash write operations (in ms)
-- CFG_FLASH_ENV_OFFSET
- Offset of envrionment data (aka NVRAM area) to the
- beginning of flash memory; for instance, to with
- bottom boot type flash chips the second sector will
- be used; in our example configuration, the offset for
- this sector is 0x8000.
-
- BE CAREFUL! Any changes to the flash layout, and some
- changes to the source code will make it necessary to
- adapt <board>/ppcboot.lds* accordingly!
-
- If you are not booting from flash, or want to have
- the environment separate from the monitor code for
- some reason, then don't define this, define
- CFG_FLASH_ENV_ADDR below. You will need to reflect
- this in your ppcboot.lds linker script.
-
-- CFG_FLASH_ENV_SIZE:
- Size of the flash sector(s) used for the environment.
- If you have very large flash sectors, keep this small
- (4K?) and define CFG_FLASH_ENV_BUF below.
-
-- CFG_FLASH_ENV_ADDR:
- Address of the non-volatile environment (usually
- within flash). This setting over-rides
- CFG_FLASH_ENV_OFFSET and is usually used if booting
- from EPROM or some other non-modifiable media, and
- hence the non-volatile area where the environment is
- stored must be separate from the area where the
- monitor boot code is stored.
-
- Before the monitor is relocated into RAM, the
- environment located at this address will be
- referenced directly (if it is valid, as indicated by
- a signature at the start of the environment - if it
- isn't valid, the default environment will *silently*
- be used). This is because until the monitor is
- relocated, the "in-memory" environment will actually
- be in ROM (in the BSS area) and therefore not valid.
-
- In other words, the environment should be considered
- to be "read-only" until the monitor is relocated.
-
- Note: once the monitor has been relocated, then it
- will complain if the default environment is used - it
- had to be silent before that because the serial
- console might not have been usable.
-
- Note2: you must edit your ppcboot.lds file to reflect
- this configuration. The label "env_offset" will not
- be defined which should provide a good warning signal
- if you forget.
-
-- CFG_FLASH_ENV_BUF:
- If this is defined, then it's value is the number of
- bytes in the flash sector where the environment is
- stored, and this much space will be reserved between
- the board info structure and the top of the stack
- (see board_init_f()).
-
- This space will be used as an intermediate buffer for
- writing the environment into flash. This allows the
- environment size (CFG_FLASH_ENV_SIZE) to be smaller
- than the size of a flash sector. Useful if you have
- huge sectors, as with the Cogent CMA302 Flash I/O
- module, which has 512KB sectors.
-
- This is only really useful if you aren't booting from
- flash (if you are, then the environment will
- automatically be in the flash) i.e.
- CFG_FLASH_ENV_ADDR is defined above.
-
-
-Many of the remaining options are named exactly as the corresponding
-Linux kernel configuration options. The intention is to make it
-easier to build a config tool - later.
+
+The following definitions that deal with the placement and management
+of environment data (variable area); in general, we support the
+following configurations:
+
+- CFG_ENV_IS_IN_FLASH:
+
+ Define this if the environment is in flash memory.
+
+ a) The environment occupies one whole flash sector, which is
+ "embedded" in the text segment with the PPCBoot code. This
+ happens usually with "bottom boot sector" or "top boot
+ sector" type flash chips, which have several smaller
+ sectors at the start or the end. For instance, such a
+ layout can have sector sizes of 8, 2x4, 16, Nx32 kB. In
+ such a case you would place the environment in one of the
+ 4 kB sectors - with PPCBoot code before and after it. With
+ "top boot sector" type flash chips, you would put the
+ environment in one of the last sectors, leaving a gap
+ between PPCBoot and the environment.
+
+ - CFG_ENV_OFFSET:
+
+ Offset of environment data (variable area) to the
+ beginning of flash memory; for instance, with bottom boot
+ type flash chips the second sector can be used: the offset
+ for this sector is given here.
+
+ CFG_ENV_OFFSET is used relative to CFG_FLASH_BASE.
+
+ - CFG_ENV_ADDR:
+
+ This is just another way to specify the start address of
+ the flash sector containing the environment (instead of
+ CFG_ENV_OFFSET).
+
+ - CFG_ENV_SECT_SIZE:
+
+ Size of the sector containing the environment.
+
+
+ b) Sometimes flash chips have few, equal sized, BIG sectors.
+ In such a case you don't want to spend a whole sector for
+ the environment.
+
+ - CFG_ENV_SIZE:
+
+ If you use this in combination with CFG_ENV_IS_IN_FLASH
+ and CFG_ENV_SECT_SIZE, you can specify to use only a part
+ of this flash sector for the environment. This saves
+ memory for the RAM copy of the environment.
+
+ It may also save flash memory if you decide to use this
+ when your environment is "embedded" within PPCBoot code,
+ since then the remainder of the flash sector could be used
+ for PPCBoot code. It should be pointed out that this is
+ STRONGLY DISCOURAGED from a robustness point of view:
+ updating the environment in flash makes it always
+ necessary to erase the WHOLE sector. If something goes
+ wrong before the contents has been restored from a copy in
+ RAM, your target system will be dead.
+
+
+BE CAREFUL! Any changes to the flash layout, and some changes to the
+source code will make it necessary to adapt <board>/ppcboot.lds*
+accordingly!
+
+
+- CFG_ENV_IS_IN_NVRAM:
+
+ Define this if you have some non-volatile memory device
+ (NVRAM, battery buffered SRAM) which you want to use for the
+ environment.
+
+ - CFG_ENV_ADDR:
+ - CFG_ENV_SIZE:
+
+ These two #defines are used to determin the memory area you
+ want to use for environment. It is assumed that this memory
+ can just be read and written to, without any special
+ provision.
+
+BE CAREFUL! The first access to the environment happens quite early
+in PPCboot initalization (when we try to get the setting of for the
+console baudrate). You *MUST* have mappend your NVRAM area then, or
+PPCBoot will hang.
+
+Please note that even with NVRAM we still use a copy of the
+environment in RAM: we could work on NVRAM directly, but we want to
+keep settings there always unmodified except somebody uses "saveenv"
+to save the current settings.
+
+
+- CFG_ENV_IS_IN_EEPROM:
+
+ Use this if you have an EEPROM or similar serial access
+ device and a driver for it.
+
+ - CFG_ENV_OFFSET:
+ - CFG_ENV_SIZE:
+
+ These two #defines specify the offset and size of the
+ environment area withon the ttal memory of your EEPROM.
+
+
+Please note that the environment is read-only as long as the monitor
+has been relocated to RAM and a RAM copy of the environment has been
+created; also, when using EEPROM you will have to use getenv_r()
+until then to read environment variables.
+
+The environment is now protected by a CRC32 checksum. Before the
+monitor is relocated into RAM, as a result of a bad CRC you will be
+working with the compiled-in default environment - *silently*!!!
+[This is necessary, because the first environment variable we need is
+the "baudrate" setting for the console - if we have a bad CRC, we
+don't have any device yet whewre we could complain.]
+
+Note: once the monitor has been relocated, then it will complain if
+the default environment is used; a new CRC is computed as sson as you
+use the "setenv" command to modify / delete / add any environment
+variable [even when you try to delete a non-existing variable!].
+
+Note2: you must edit your ppcboot.lds file to reflect this
+configuration.
+
+
+Many of the options are named exactly as the corresponding Linux
+kernel configuration options. The intention is to make it easier to
+build a config tool - later.
Low Level (hardware related) configuration options:
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- ppc4xx/start.o (.text)
- ppc4xx/traps.o (.text)
- ppc4xx/interrupts.o (.text)
- ppc4xx/serial.o (.text)
- ppc4xx/cpu_init.o (.text)
- ppc4xx/speed.o (.text)
+ cpu/ppc4xx/start.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
ppc/crc32.o (.text)
ppc/extable.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
#include <ppcboot.h>
-#include <cogent/dipsw.h>
+#include <board/cogent/dipsw.h>
unsigned char
dipsw_raw(void)
*/
#include <ppcboot.h>
-#include <cogent/flash.h>
+#include <board/cogent/flash.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined(CFG_FLASH_ENV_BUF)
CFG_FLASH_ENV_ADDR + CFG_FLASH_ENV_BUF - 1,
#else
- CFG_FLASH_ENV_ADDR + CFG_FLASH_ENV_SIZE - 1,
+ CFG_FLASH_ENV_ADDR + CFG_ENV_SIZE - 1,
#endif
&flash_info[0]);
#endif
#include <ppcboot.h>
#include <stdarg.h>
-#include <cogent/lcd.h>
+#include <board/cogent/lcd.h>
static char lines[2][LCD_LINE_LENGTH+1];
static int curline;
*/
#include <ppcboot.h>
-#include <cogent/dipsw.h>
-#include <cogent/lcd.h>
-#include <cogent/rtc.h>
-#include <cogent/par.h>
-#include <cogent/pci.h>
+#include <board/cogent/dipsw.h>
+#include <board/cogent/lcd.h>
+#include <board/cogent/rtc.h>
+#include <board/cogent/par.h>
+#include <board/cogent/pci.h>
/* ------------------------------------------------------------------------- */
.text :
{
*(.text)
+ common/environment.o(.text)
*(.fixup)
*(.got1)
}
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
*/
#include <ppcboot.h>
-#include <cogent/serial.h>
+#include <board/cogent/serial.h>
#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR) && \
((defined(CONFIG_8xx) && defined(CONFIG_8xx_CONS_NONE)) || \
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- ppc4xx/start.o (.text)
- ppc4xx/traps.o (.text)
- ppc4xx/interrupts.o (.text)
- ppc4xx/serial.o (.text)
- ppc4xx/cpu_init.o (.text)
- ppc4xx/speed.o (.text)
- ppc4xx/405gp_enet.o (.text)
+ cpu/ppc4xx/start.o (.text)
+ cpu/ppc4xx/traps.o (.text)
+ cpu/ppc4xx/interrupts.o (.text)
+ cpu/ppc4xx/serial.o (.text)
+ cpu/ppc4xx/cpu_init.o (.text)
+ cpu/ppc4xx/speed.o (.text)
+ cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
ppc/crc32.o (.text)
ppc/extable.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
- mpc8xx/traps.o (.text)
- mpc8xx/interrupts.o (.text)
- mpc8xx/serial.o (.text)
- mpc8xx/cpu_init.o (.text)
- mpc8xx/speed.o (.text)
+ cpu/mpc8xx/start.o (.text)
+ cpu/mpc8xx/traps.o (.text)
+ cpu/mpc8xx/interrupts.o (.text)
+ cpu/mpc8xx/serial.o (.text)
+ cpu/mpc8xx/cpu_init.o (.text)
+ cpu/mpc8xx/speed.o (.text)
common/dlmalloc.o (.text)
ppc/crc32.o (.text)
ppc/zlib.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
- mpc8xx/traps.o (.text)
- mpc8xx/interrupts.o (.text)
- mpc8xx/cpu.o (.text)
- mpc8xx/cpu_init.o (.text)
- mpc8xx/speed.o (.text)
- mpc8xx/serial.o (.text)
+ cpu/mpc8xx/start.o (.text)
+ cpu/mpc8xx/traps.o (.text)
+ cpu/mpc8xx/interrupts.o (.text)
+ cpu/mpc8xx/cpu.o (.text)
+ cpu/mpc8xx/cpu_init.o (.text)
+ cpu/mpc8xx/speed.o (.text)
+ cpu/mpc8xx/serial.o (.text)
ppc/extable.o (.text)
ppc/ppcstring.o (.text)
ppc/string.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
/*
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/ppcstring.o (.text)
ppc/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/ppcstring.o (.text)
ppc/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/ppcstring.o (.text)
- mpc8xx/start.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
ppc/zlib.o (.text)
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# Multidata HERMES-PRO ISDN Routers
+#
+
+TEXT_BASE = 0xFE000000
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+typedef volatile unsigned char vu_char;
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET 0x01
+#define FLAG_PROTECT_CLEAR 0x02
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+
+int flash_write (uchar *, ulong, ulong);
+flash_info_t *addr2info (ulong);
+
+static int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+static int write_byte (flash_info_t *info, ulong dest, uchar data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+static int flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ unsigned long size;
+ int i;
+
+ /* Init: no FLASHes known */
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size, size<<20);
+ }
+
+ /* Remap FLASH according to real size */
+ memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+ memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) |
+ (memctl->memc_br0 & ~(BR_BA_MSK));
+
+ /* Re-do sizing to get full correct info */
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+
+ flash_info[0].size = size;
+
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ * Check or set protection status for monitor sectors
+ *
+ * The monitor always occupies the _first_ part of the _first_ Flash bank.
+ */
+static int flash_protect (int flag, ulong from, ulong to, flash_info_t *info)
+{
+ ulong b_end = info->start[0] + info->size - 1; /* bank end address */
+ int rc = 0;
+ int first = -1;
+ int last = -1;
+ int i;
+
+ if (to < info->start[0]) {
+ return (0);
+ }
+
+ for (i=0; i<info->sector_count; ++i) {
+ ulong end; /* last address in current sect */
+ short s_end;
+
+ s_end = info->sector_count - 1;
+
+ end = (i == s_end) ? b_end : info->start[i + 1] - 1;
+
+ if (from > end) {
+ continue;
+ }
+ if (to < info->start[i]) {
+ continue;
+ }
+
+ if (from == info->start[i]) {
+ first = i;
+ if (last < 0) {
+ last = s_end;
+ }
+ }
+ if (to == end) {
+ last = i;
+ if (first < 0) {
+ first = 0;
+ }
+ }
+ }
+
+ for (i=first; i<=last; ++i) {
+ if (flag & FLAG_PROTECT_CLEAR) {
+ info->protect[i] = 0;
+ } else if (flag & FLAG_PROTECT_SET) {
+ info->protect[i] = 1;
+ }
+ if (info->protect[i]) {
+ rc = 1;
+ }
+ }
+ return (rc);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ /* set up sector start adress table */
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD: printf ("AMD "); break;
+ case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
+ break;
+ case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
+ break;
+ case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ uchar value;
+ vu_char *caddr = (vu_char *)addr;
+ ulong base = (ulong)addr;
+
+
+ /* Write auto select command: read Manufacturer ID */
+ caddr[0x0AAA] = 0xAA;
+ caddr[0x0555] = 0x55;
+ caddr[0x0AAA] = 0x90;
+
+ value = caddr[0];
+ switch (value) {
+ case (AMD_MANUFACT & 0xFF):
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+ case (FUJ_MANUFACT & 0xFF):
+ info->flash_id = FLASH_MAN_FUJ;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = caddr[2]; /* device ID */
+
+ switch (value) {
+ case (AMD_ID_LV400T & 0xFF):
+ info->flash_id += FLASH_AM400T;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 512 kB */
+
+ case (AMD_ID_LV400B & 0xFF):
+ info->flash_id += FLASH_AM400B;
+ info->sector_count = 11;
+ info->size = 0x00080000;
+ break; /* => 512 kB */
+
+ case (AMD_ID_LV800T & 0xFF):
+ info->flash_id += FLASH_AM800T;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (AMD_ID_LV800B & 0xFF):
+ info->flash_id += FLASH_AM800B;
+ info->sector_count = 19;
+ info->size = 0x00100000;
+ break; /* => 1 MB */
+
+ case (AMD_ID_LV160T & 0xFF):
+ info->flash_id += FLASH_AM160T;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+
+ case (AMD_ID_LV160B & 0xFF):
+ info->flash_id += FLASH_AM160B;
+ info->sector_count = 35;
+ info->size = 0x00200000;
+ break; /* => 2 MB */
+#if 0 /* enable when device IDs are available */
+ case (AMD_ID_LV320T & 0xFF):
+ info->flash_id += FLASH_AM320T;
+ info->sector_count = 67;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+
+ case (AMD_ID_LV320B & 0xFF):
+ info->flash_id += FLASH_AM320B;
+ info->sector_count = 67;
+ info->size = 0x00400000;
+ break; /* => 4 MB */
+#endif
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start adress table */
+ if (info->flash_id & FLASH_BTYPE) {
+ /* set sector offsets for bottom boot block type */
+ info->start[0] = base + 0x00000000;
+ info->start[1] = base + 0x00004000;
+ info->start[2] = base + 0x00006000;
+ info->start[3] = base + 0x00008000;
+ for (i = 4; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00010000) - 0x00030000;
+ }
+ } else {
+ /* set sector offsets for top boot block type */
+ i = info->sector_count - 1;
+ info->start[i--] = base + info->size - 0x00004000;
+ info->start[i--] = base + info->size - 0x00006000;
+ info->start[i--] = base + info->size - 0x00008000;
+ for (; i >= 0; i--) {
+ info->start[i] = base + i * 0x00010000;
+ }
+ }
+
+ /* check for protected sectors */
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection: D0 = 1 if protected */
+ caddr = (volatile unsigned char *)(info->start[i]);
+ info->protect[i] = caddr[4] & 1;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ caddr = (vu_char *)info->start[0];
+
+ *caddr = 0xF0; /* reset bank */
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ vu_char *addr = (vu_char*)(info->start[0]);
+ int flag, prot, sect, l_sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return;
+ }
+
+ if ((info->flash_id == FLASH_UNKNOWN) ||
+ (info->flash_id > FLASH_AMD_COMP)) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ l_sect = -1;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0AAA] = 0xAA;
+ addr[0x0555] = 0x55;
+ addr[0x0AAA] = 0x80;
+ addr[0x0AAA] = 0xAA;
+ addr[0x0555] = 0x55;
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (vu_char*)(info->start[sect]);
+ addr[0] = 0x30;
+ l_sect = sect;
+ }
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ /*
+ * We wait for the last triggered sector
+ */
+ if (l_sect < 0)
+ goto DONE;
+
+ start = get_timer (0);
+ last = start;
+ addr = (vu_char*)(info->start[l_sect]);
+ while ((addr[0] & 0x80) != 0x80) {
+ if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ return;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+
+DONE:
+ /* reset to read mode */
+ addr = (vu_char *)info->start[0];
+ addr[0] = 0xF0; /* reset bank */
+
+ printf (" done\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+flash_info_t *addr2info (ulong addr)
+{
+ flash_info_t *info;
+ int i;
+
+ for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
+ if ((addr >= info->start[0]) &&
+ (addr < (info->start[0] + info->size)) ) {
+ return (info);
+ }
+ }
+
+ return (NULL);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ * Make sure all target addresses are within Flash bounds,
+ * and no protected sectors are hit.
+ * Returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - target range includes protected sectors
+ * 8 - target address not in Flash memory
+ */
+int flash_write (uchar *src, ulong addr, ulong cnt)
+{
+ int i;
+ ulong end = addr + cnt - 1;
+ flash_info_t *info_first = addr2info (addr);
+ flash_info_t *info_last = addr2info (end );
+ flash_info_t *info;
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ if (!info_first || !info_last) {
+ return (8);
+ }
+
+ for (info = info_first; info <= info_last; ++info) {
+ ulong b_end = info->start[0] + info->size; /* bank end addr */
+ short s_end = info->sector_count - 1;
+ for (i=0; i<info->sector_count; ++i) {
+ ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
+
+ if ((end >= info->start[i]) && (addr < e_addr) &&
+ (info->protect[i] != 0) ) {
+ return (4);
+ }
+ }
+ }
+
+ /* finally write data to flash */
+ for (info = info_first; info <= info_last && cnt>0; ++info) {
+ ulong len;
+
+ len = info->start[0] + info->size - addr;
+ if (len > cnt)
+ len = cnt;
+ if ((i = write_buff(info, src, addr, len)) != 0) {
+ return (i);
+ }
+ cnt -= len;
+ addr += len;
+ src += len;
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+static int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ int rc;
+
+ while (cnt > 0) {
+ if ((rc = write_byte(info, addr++, *src++)) != 0) {
+ return (rc);
+ }
+ --cnt;
+ }
+
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte (flash_info_t *info, ulong dest, uchar data)
+{
+ vu_char *addr = (vu_char*)(info->start[0]);
+ ulong start;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*((vu_char *)dest) & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr[0x0AAA] = 0xAA;
+ addr[0x0555] = 0x55;
+ addr[0x0AAA] = 0xA0;
+
+ *((vu_char *)dest) = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ return (1);
+ }
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <commproc.h>
+#include "mpc8xx.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+static ulong board_init (void);
+static void send_smi_frame(volatile scc_t *sp, volatile cbd_t *bd, uchar *msg);
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+ /*
+ * Single Read. (Offset 0 in UPMA RAM)
+ */
+ 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+ 0x1ff77c47, /* last */
+ /*
+ * SDRAM Initialization (offset 5 in UPMA RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0x1fe77c35, 0xffaffc34, 0x1fa57c35, /* last */
+ /*
+ * Burst Read. (Offset 8 in UPMA RAM)
+ */
+ 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+ 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPMA RAM)
+ */
+ 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPMA RAM)
+ */
+ 0x1f07fc04, 0xeeaebc00, 0x10ad4c00, 0xf0afcc00,
+ 0xf0afcc00, 0xe1bb8c06, 0x1ff77c47, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPMA RAM)
+ */
+ 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ 0xfffffc84, 0xfffffc07, /* last */
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPMA RAM)
+ */
+ 0x7ffffc07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test ID string (HERMES...)
+ *
+ * Return code for board revision and network speed
+ */
+
+int checkboard (void)
+{
+ unsigned char *s = getenv("serial#");
+ unsigned char *e;
+ int rev_speed;
+
+ if (!s || strncmp(s, "HERMES", 6)) {
+ puts ("### No HW ID - assuming HERMES-PRO");
+ } else {
+ for (e=s; *e; ++e) {
+ if (*e == ' ')
+ break;
+ }
+
+ for ( ; s<e; ++s) {
+ putc (*s);
+ }
+ }
+
+ rev_speed = board_init ();
+
+ printf (" Rev. %d.x\n", (rev_speed >> 16));
+
+ return (rev_speed);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size, size8, size9;
+
+ upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+ /*
+ * Preliminary prescaler for refresh
+ */
+ memctl->memc_mptpr = 0x0400;
+
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller banks 1 to the SDRAM banks at preliminary address
+ */
+ memctl->memc_or1 = CFG_OR1_PRELIM;
+ memctl->memc_br1 = CFG_BR1_PRELIM;
+
+ /* HERMES-PRO boards have only one bank SDRAM */
+
+
+ udelay(200);
+
+ /* perform SDRAM initializsation sequence */
+
+ memctl->memc_mamr = 0xD0802114;
+ memctl->memc_mcr = 0x80002105;
+ udelay(1);
+ memctl->memc_mamr = 0xD0802118;
+ memctl->memc_mcr = 0x80002130;
+ udelay(1);
+ memctl->memc_mamr = 0xD0802114;
+ memctl->memc_mcr = 0x80002106;
+
+ udelay (1000);
+
+ /*
+ * Check Bank 0 Memory Size for re-configuration
+ *
+ * try 8 column mode
+ */
+ size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+
+ udelay (1000);
+
+ /*
+ * try 9 column mode
+ */
+ size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+
+ if (size8 < size9) { /* leave configuration at 9 columns */
+ size = size9;
+/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
+ } else { /* back to 8 columns */
+ size = size8;
+ memctl->memc_mamr = CFG_MAMR_8COL;
+ udelay(500);
+/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
+ }
+
+ udelay (1000);
+
+ memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
+ memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+ udelay(10000);
+
+ return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile long int *addr;
+ long int cnt, val;
+
+ memctl->memc_mamr = mamr_value;
+
+ for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ *addr = ~cnt;
+ }
+
+ /* write 0 to base address */
+ addr = base;
+ *addr = 0;
+
+ /* check at base address */
+ if ((val = *addr) != 0) {
+ return (0);
+ }
+
+ for (cnt = 1; ; cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ val = *addr;
+
+ if (val != (~cnt)) {
+ return (cnt * sizeof(long));
+ }
+ }
+ /* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+#define PB_LED_3 0x00020000 /* Status LED's */
+#define PB_LED_2 0x00010000
+#define PB_LED_1 0x00008000
+#define PB_LED_0 0x00004000
+
+#define PB_LED_ALL (PB_LED_0 | PB_LED_1 | PB_LED_2 | PB_LED_3)
+
+#define PC_REP_SPD1 0x00000800
+#define PC_REP_SPD0 0x00000400
+
+#define PB_RESET_2081 0x00000020 /* Reset PEB2081 */
+
+#define PB_MAI_4 0x00000010 /* Configuration */
+#define PB_MAI_3 0x00000008
+#define PB_MAI_2 0x00000004
+#define PB_MAI_1 0x00000002
+#define PB_MAI_0 0x00000001
+
+#define PB_MAI_ALL (PB_MAI_0 | PB_MAI_1 | PB_MAI_2 | PB_MAI_3 | PB_MAI_4)
+
+
+#define PC_REP_MGRPRS 0x0200
+#define PC_REP_SPD 0x0040 /* Select 100 Mbps */
+#define PC_REP_RES 0x0004
+#define PC_BIT14 0x0002 /* ??? */
+#define PC_BIT15 0x0001 /* ??? ENDSL ?? */
+
+/* ------------------------------------------------------------------------- */
+
+static ulong board_init (void)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ ulong reg, revision, speed;
+ int ethspeed;
+ char *s;
+
+ if ((s = getenv ("ethspeed")) != NULL) {
+ if (strcmp(s, "100") == 0) {
+ ethspeed = 100;
+ } else if (strcmp(s, "10") == 0) {
+ ethspeed = 10;
+ } else {
+ ethspeed = 0;
+ }
+ } else {
+ ethspeed = 0;
+ }
+
+ /* Configure Port B Output Pins => 0x0003cc3F */
+ reg = PB_LED_ALL | PC_REP_SPD1 | PC_REP_SPD0 | PB_RESET_2081 | PB_MAI_ALL;
+ immr->im_cpm.cp_pbpar &= ~reg;
+ immr->im_cpm.cp_pbodr &= ~reg;
+ immr->im_cpm.cp_pbdat &= ~reg; /* all 0 */
+ immr->im_cpm.cp_pbdir |= reg;
+
+ /* Check hardware revision */
+ if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) {
+ /*
+ * Revision 3.x hardware
+ */
+ revision = 3;
+
+ immr->im_ioport.iop_pcdat = 0x0240;
+ immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES |
+ PC_BIT14); /* = 0x0246 */
+ immr->im_ioport.iop_pcdat |= PC_REP_RES;
+ } else {
+ immr->im_ioport.iop_pcdat = 0x0002;
+ immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES |
+ PC_BIT14 | PC_BIT15); /* = 0x0207 */
+
+ if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) {
+ /*
+ * Revision 2.x hardware: PC9 connected to PB21
+ */
+ revision = 2;
+
+ if (ethspeed == 0) {
+ /* both 10 and 100 Mbps allowed:
+ * select 10 Mbps and autonegotiation
+ */
+puts (" [10+100]");
+ immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
+ speed = 10;
+ } else if (ethspeed == 10) {
+ /* we are asked for 10 Mbps,
+ * so select 10 Mbps
+ */
+puts (" [10]");
+ immr->im_cpm.cp_pbdat = 0; /* ??? */
+ speed = 10;
+ } else {
+ /* anything else:
+ * select 100 Mbps
+ */
+puts (" [100]");
+ immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
+ /* SPD1:SPD0 = 1:1 - 100 Mbps */
+ speed = 100;
+ }
+ immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14);
+
+ /* must be run from RAM */
+ /* start_lxt980 (speed); */
+ /*************************/
+ } else {
+ /*
+ * Revision 1.x hardware
+ */
+ revision = 1;
+
+ immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14; /* = 0x0202 */
+ immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES |
+ PC_BIT14 | PC_BIT15); /* = 0x0247 */
+
+ if (ethspeed == 0) {
+ /* both 10 and 100 Mbps allowed:
+ * select 100 Mbps and autonegotiation
+ */
+puts (" [10+100]");
+ immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
+ immr->im_ioport.iop_pcdat |= PC_REP_SPD;
+ } else if (ethspeed == 10) {
+ /* we are asked for 10 Mbps,
+ * so select 10 Mbps
+ */
+puts (" [10]");
+ immr->im_cpm.cp_pbdat = PC_REP_SPD0; /* SPD1:SPD0 = 0:1 - 10 Mbps */
+ } else {
+ /* anything else:
+ * select 100 Mbps
+ */
+puts (" [100]");
+ immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
+ /* SPD1:SPD0 = 1:1 - 100 Mbps */
+ immr->im_ioport.iop_pcdat |= PC_REP_SPD;
+ }
+
+ immr->im_ioport.iop_pcdat |= PC_REP_RES;
+ }
+ }
+ hermes_set_led (0);
+
+ return ((revision << 16) | (speed & 0xFFFF));
+}
+
+/* ------------------------------------------------------------------------- */
+
+#define SCC_SM 1 /* Index => SCC2 */
+#define PROFF PROFF_SCC2
+
+#define SMI_MSGLEN 8 /* Length of SMI Messages */
+
+#define PHYGPCR_ADDR 0x109 /* Port Enable */
+#define PHYPCR_ADDR 0x132 /* PHY Port Control Reg. (port 1) */
+#define LEDPCR_ADDR 0x141 /* LED Port Control Reg. */
+#define RPRESET_ADDR 0x144 /* Repeater Reset */
+
+#define PHYPCR_SPEED 0x2000 /* on for 100 Mbps, off for 10 Mbps */
+#define PHYPCR_AN 0x1000 /* on to enable Auto-Negotiation */
+#define PHYPCR_REST_AN 0x0200 /* on to restart Auto-Negotiation */
+#define PHYPCR_FDX 0x0100 /* on for Full Duplex, off for HDX */
+#define PHYPCR_COLT 0x0080 /* on to enable COL signal test */
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Must run from RAM:
+ * uses parameter RAM area which is used for stack while running from ROM
+ */
+void hermes_start_lxt980 (int speed)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile cpm8xx_t *cp = (cpm8xx_t *)&(immr->im_cpm);
+ volatile scc_t *sp = (scc_t *)&(cp->cp_scc[SCC_SM]);
+ volatile cbd_t *bd;
+ volatile hdlc_pram_t *hp;
+ uchar smimsg[SMI_MSGLEN];
+ ushort phypcrval;
+ uint bd_off;
+ int pnr;
+
+ printf (" LXT9880: %3d Mbps\n", speed);
+
+ immr->im_ioport.iop_paodr |= 0x0008; /* init PAODR: PA12 (TXD2) open drain */
+ immr->im_ioport.iop_papar |= 0x400c; /* init PAPAR: TXD2, RXD2, BRGO4 */
+ immr->im_ioport.iop_padir &= 0xbff3; /* init PADIR: BRGO4 */
+ immr->im_ioport.iop_padir |= 0x4000;
+
+ /* get temporary BD; no need for permanent alloc */
+ bd_off = m8xx_cpm_dpbase_align(8);
+
+ bd = (cbd_t *)(immr->im_cpm.cp_dpmem + bd_off);
+
+ bd->cbd_bufaddr = 0;
+ bd->cbd_datlen = 0;
+ bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC ;
+
+ /* init. baudrate generator BRG4 */
+ cp->cp_brgc4 = (0x00010000 | (50<<1)); /* output 1 MHz */
+
+ cp->cp_sicr &= 0xFFFF00FF; /* SICR: mask SCC2 */
+ cp->cp_sicr |= 0x00001B00; /* SICR: SCC2 clk BRG4 */
+
+ /* init SCC_SM register */
+ sp->scc_psmr = 0x0000; /* init PSMR: no additional flags */
+ sp->scc_todr = 0x0000;
+ sp->scc_dsr = 0x7e7e;
+
+ /* init. SCC_SM parameter area */
+ hp = (hdlc_pram_t *)&cp->cp_dparam[PROFF];
+
+ hp->tbase = bd_off; /* offset from beginning of DPRAM */
+
+ hp->rfcr = 0x18;
+ hp->tfcr = 0x18;
+ hp->mrblr = 10;
+
+ hp->c_mask = 0x0000f0b8;
+ hp->c_pres = 0x0000ffff;
+
+ hp->disfc = 0;
+ hp->crcec = 0;
+ hp->abtsc = 0;
+ hp->nmarc = 0;
+ hp->retrc = 0;
+
+ hp->mflr = 10;
+
+ hp->rfthr = 1;
+
+ hp->hmask = 0;
+ hp->haddr1 = 0;
+ hp->haddr2 = 0;
+ hp->haddr3 = 0;
+ hp->haddr4 = 0;
+
+ cp->cp_cpcr = SCC_SM<<6 | 0x0001; /* SCC_SM: init TX/RX params */
+ while (cp->cp_cpcr & CPM_CR_FLG)
+ ;
+
+ /* clear all outstanding SCC events */
+ sp->scc_scce = ~0;
+
+ /* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */
+ sp->scc_gsmrh = 0;
+ sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 |
+ SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC ;
+
+#if 0
+ smimsg[0] = 0x00; /* CHIP/HUB ID */
+ smimsg[1] = 0x38; /* WRITE CMD */
+ smimsg[2] = (RPRESET_ADDR<<4) & 0xf0;
+ smimsg[3] = RPRESET_ADDR>>4;
+ smimsg[4] = 0x01;
+ smimsg[5] = 0x00;
+ smimsg[6] = 0x00;
+ smimsg[7] = 0x00;
+
+ send_smi_frame (sp, bd, smimsg);
+#endif
+
+ smimsg[0] = 0x7f; /* BROADCAST */
+ smimsg[1] = 0x34; /* ASSIGN HUB ID */
+ smimsg[2] = 0x00;
+ smimsg[3] = 0x00;
+ smimsg[4] = 0x00; /* HUB ID = 0 */
+ smimsg[5] = 0x00;
+ smimsg[6] = 0x00;
+ smimsg[7] = 0x00;
+
+ send_smi_frame (sp, bd, smimsg);
+
+ smimsg[0] = 0x7f; /* BROADCAST */
+ smimsg[1] = 0x3c; /* SET ARBOUT TO 0 */
+ smimsg[2] = 0x00; /* ADDRESS = 0 */
+ smimsg[3] = 0x00;
+ smimsg[4] = 0x00; /* DATA = 0 */
+ smimsg[5] = 0x00;
+ smimsg[6] = 0x00;
+ smimsg[7] = 0x00;
+
+ send_smi_frame (sp, bd, smimsg);
+
+ if (speed == 100) {
+ phypcrval = PHYPCR_SPEED; /* 100 MBIT, disable autoneg. */
+ } else {
+ phypcrval = 0; /* 10 MBIT, disable autoneg. */
+ }
+
+ /* send MSGs */
+ for (pnr=0; pnr<8; pnr++) {
+ smimsg[0] = 0x00; /* CHIP/HUB ID */
+ smimsg[1] = 0x38; /* WRITE CMD */
+ smimsg[2] = ((PHYPCR_ADDR + pnr)<<4) & 0xf0;
+ smimsg[3] = (PHYPCR_ADDR + pnr)>>4;
+ smimsg[4] = (unsigned char)(phypcrval & 0xff);
+ smimsg[5] = (unsigned char)(phypcrval>>8);
+ smimsg[6] = 0x00;
+ smimsg[7] = 0x00;
+
+ send_smi_frame (sp, bd, smimsg);
+ }
+
+ smimsg[0] = 0x00; /* CHIP/HUB ID */
+ smimsg[1] = 0x38; /* WRITE CMD */
+ smimsg[2] = (PHYGPCR_ADDR<<4) & 0xf0;
+ smimsg[3] = PHYGPCR_ADDR>>4;
+ smimsg[4] = 0xff; /* enable port 1-8 */
+ smimsg[5] = 0x01; /* enable MII1 (0x01) */
+ smimsg[6] = 0x00;
+ smimsg[7] = 0x00;
+
+ send_smi_frame (sp, bd, smimsg);
+
+ smimsg[0] = 0x00; /* CHIP/HUB ID */
+ smimsg[1] = 0x38; /* WRITE CMD */
+ smimsg[2] = (LEDPCR_ADDR<<4) & 0xf0;
+ smimsg[3] = LEDPCR_ADDR>>4;
+ smimsg[4] = 0xaa; /* Port 1-8 Conf.bits = 10 (Hardware control) */
+ smimsg[5] = 0xaa;
+ smimsg[6] = 0x00;
+ smimsg[7] = 0x00;
+
+ send_smi_frame (sp, bd, smimsg);
+
+ /*
+ * Disable Transmitter (so that we can free the BD, too)
+ */
+ sp->scc_gsmrl &= ~SCC_GSMRL_ENT;
+}
+
+/* ------------------------------------------------------------------------- */
+
+static void send_smi_frame (volatile scc_t *sp, volatile cbd_t *bd, uchar *msg)
+{
+#ifdef DEBUG
+ unsigned hub, chip, cmd, length, addr;
+
+ hub = msg[0] & 0x1F;
+ chip = msg[0] >> 5;
+ cmd = msg[1] & 0x1F;
+ length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3);
+ addr = (msg[2] >> 4) | (msg[3] << 4);
+
+ printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: "
+ "%02x %02x %02x %02x\n",
+ hub, chip, cmd, length, addr,
+ msg[4], msg[5], msg[6], msg[7]);
+#endif /* DEBUG */
+
+ bd->cbd_bufaddr = (uint)msg;
+ bd->cbd_datlen = SMI_MSGLEN;
+ bd->cbd_sc |= BD_SC_READY;
+
+ /* wait for msg transmitted */
+ while ((sp->scc_scce & 0x0002) == 0)
+ ;
+ /* clear all events */
+ sp->scc_scce = ~0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void hermes_set_led (int code)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ code ^= 0x0F;
+ code = (code & 0x0F) << 14;
+ immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | code;
+}
+
+/* ------------------------------------------------------------------------- */
+
+void hermes_show_led_err (int code)
+{
+ int i;
+
+ for (;;) {
+ hermes_set_led (code);
+ for (i=0;i<100000;i++);
+ hermes_set_led (0);
+ for (i=0;i<100000;i++);
+ }
+}
+
+/* ------------------------------------------------------------------------- */
+
+void hermes_flash_led (void)
+{
+ int i;
+ int led=0;
+
+ for (;;) {
+ hermes_set_led (1 << led);
+ for (i=0;i<100000;i++);
+ led = (++led) & 3;
+ }
+}
+
+/* ------------------------------------------------------------------------- */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/ppcstring.o (.text)
+ cpu/mpc8xx/interrupts.o (.text)
+ ppc/time.o (.text)
+ ppc/ticks.o (.text)
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ ppc/ppcstring.o (.text)
+ cpu/mpc8xx/interrupts.o (.text)
+ ppc/time.o (.text)
+ ppc/ticks.o (.text)
+ . = env_offset;
+ common/environment.o(.text)
+
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8260/start.o (.text)
+ cpu/mpc8260/start.o (.text)
/*
common/dlmalloc.o (.text)
ppc/ppcstring.o (.text)
ppc/zlib.o (.text)
. = env_offset;
- common/environment.o(.text)
*/
+ common/environment.o(.text)
*(.text)
*(.fixup)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS = $(BOARD).o flash.o eeprom.o
+
+$(LIB): .depend $(OBJS)
+ $(AR) crv $@ $^
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+sinclude .depend
+
+#########################################################################
--- /dev/null
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MicroSys IP860 VMEBus Systems
+#
+
+TEXT_BASE = 0x10000000
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+/*-----------------------------------------------------------------------
+ * Definitions
+ */
+
+#define PB_SCL 0x00000020 /* PB 26 */
+#define PB_SDA 0x00000010 /* PB 27 */
+
+#define SET_PB_BIT(bit) do { \
+ immr->im_cpm.cp_pbdir |= bit; /* output */ \
+ immr->im_cpm.cp_pbdat |= bit; /* set 1 */ \
+ udelay (5); \
+ } while (0)
+
+#define RESET_PB_BIT(bit) do { \
+ immr->im_cpm.cp_pbdir |= bit; /* output */ \
+ immr->im_cpm.cp_pbdat &= ~bit; /* set 8 */ \
+ udelay (5); \
+ } while (0)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static void send_start (void);
+static void send_stop (void);
+#if 0
+static void send_ack (void);
+#endif
+static void send_ack1 (void);
+static void rcv_ack (void);
+static void send_data_1 (void);
+static void send_data_0 (void);
+static void read_addr (uchar addr);
+static void write_addr (uchar addr);
+static int read_bit (void);
+static uchar read_byte (void);
+static void write_byte (uchar byte);
+
+void eeprom_init (void);
+void eeprom_read (unsigned offset, uchar *buffer, unsigned cnt);
+void eeprom_write (unsigned offset, uchar *buffer, unsigned cnt);
+
+/*-----------------------------------------------------------------------
+ * START: High -> Low on SDA while SCL is High
+ */
+static void send_start (void)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ SET_PB_BIT (PB_SCL);
+ RESET_PB_BIT (PB_SDA);
+}
+
+/*-----------------------------------------------------------------------
+ * STOP: Low -> High on SDA while SCL is High
+ */
+static void send_stop (void)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ RESET_PB_BIT (PB_SDA);
+ SET_PB_BIT (PB_SCL);
+ SET_PB_BIT (PB_SDA);
+ udelay (5);
+}
+
+/*-----------------------------------------------------------------------
+ */
+#if 0
+static void send_ack (void)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ RESET_PB_BIT (PB_SCL);
+ RESET_PB_BIT (PB_SDA);
+ SET_PB_BIT (PB_SCL);
+ udelay (5);
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+static void send_ack1 (void)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ RESET_PB_BIT (PB_SCL);
+ SET_PB_BIT (PB_SDA);
+ SET_PB_BIT (PB_SCL);
+ udelay (5);
+ RESET_PB_BIT (PB_SCL);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void rcv_ack (void)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ RESET_PB_BIT (PB_SCL);
+
+ immr->im_cpm.cp_pbdir &= ~PB_SDA; /* input */
+ udelay (10);
+ while (immr->im_cpm.cp_pbdat & PB_SDA)
+ ;
+ udelay (5);
+ SET_PB_BIT (PB_SCL);
+ RESET_PB_BIT (PB_SCL);
+ SET_PB_BIT (PB_SDA);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void send_data_1 (void)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ RESET_PB_BIT (PB_SCL);
+ SET_PB_BIT (PB_SDA);
+ SET_PB_BIT (PB_SCL);
+ udelay (5);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void send_data_0 (void)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ RESET_PB_BIT (PB_SCL);
+ RESET_PB_BIT (PB_SDA);
+ SET_PB_BIT (PB_SCL);
+ udelay (5);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static void read_addr (uchar addr)
+{
+ int i;
+
+ addr = (addr << 1) | 0xA1;
+ for (i=0; i<8; ++i) {
+ if (addr & 0x80) {
+ send_data_1 ();
+ } else {
+ send_data_0 ();
+ }
+ addr <<= 1;
+ }
+
+ rcv_ack ();
+}
+
+/*-----------------------------------------------------------------------
+ * addr & 0xF0 -> 0xA0 = Device Type Identifier
+ * addr & 0x0E -> bank_num << 1
+ * addr & 0x01 -> 1 = read, 0 = write
+ */
+static void write_addr (uchar addr)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ addr = (addr << 1) | 0xA0;
+
+ for (;;) {
+ uchar a = addr;
+ uint i;
+
+ send_start ();
+
+ for (i=0; i<8; ++i) {
+ if (a & 0x80) {
+ send_data_1 ();
+ } else {
+ send_data_0 ();
+ }
+ a <<= 1;
+ }
+
+ RESET_PB_BIT (PB_SCL);
+
+ immr->im_cpm.cp_pbdir &= ~PB_SDA; /* input */
+ udelay (10);
+
+ i = immr->im_cpm.cp_pbdat;
+ udelay (5);
+ SET_PB_BIT (PB_SCL);
+ RESET_PB_BIT (PB_SCL);
+ SET_PB_BIT (PB_SDA);
+
+ if ((i & PB_SDA) == 0)
+ break;
+
+ send_stop();
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int read_bit (void)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ int bit;
+
+ immr->im_cpm.cp_pbdir &= ~PB_SDA; /* input */
+ udelay (5);
+ RESET_PB_BIT (PB_SCL);
+ udelay (5);
+ SET_PB_BIT (PB_SCL);
+ bit = (immr->im_cpm.cp_pbdat & PB_SDA) ? 1 : 0;
+ udelay (5);
+ return (bit);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static uchar read_byte (void)
+{
+ uchar byte = 0;
+ int i;
+
+ for (i=0; i<8; ++i) {
+ byte = (byte << 1) | read_bit();
+ }
+ send_ack1 ();
+
+ return byte;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void write_byte (uchar byte)
+{
+ int i;
+ for (i=0; i<8; ++i) {
+ if (byte & 0x80) {
+ send_data_1 ();
+ } else {
+ send_data_0 ();
+ }
+ byte <<= 1;
+ }
+ rcv_ack();
+}
+
+/*-----------------------------------------------------------------------
+ */
+void eeprom_init (void)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+ immr->im_cpm.cp_pbpar &= ~(PB_SCL | PB_SDA); /* GPIO */
+ immr->im_cpm.cp_pbodr |= (PB_SCL | PB_SDA); /* Open Drain Output */
+
+ RESET_PB_BIT (PB_SCL);
+ RESET_PB_BIT (PB_SDA);
+ SET_PB_BIT (PB_SCL);
+ SET_PB_BIT (PB_SDA); /* stop condition */
+ udelay (25);
+}
+
+/*-----------------------------------------------------------------------
+ */
+void eeprom_read (unsigned offset, uchar *buffer, unsigned cnt)
+{
+ unsigned i, blk_off, blk_num;
+
+ for (i=0; i<cnt; ++i) {
+ blk_num = (offset + i) >> 8;
+ blk_off = (offset + i) & 0xFF;
+
+ write_addr (blk_num);
+ write_byte (blk_off);
+ send_start ();
+ read_addr (blk_num);
+ *buffer++ = read_byte();
+ send_stop ();
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void eeprom_write (unsigned offset, uchar *buffer, unsigned cnt)
+{
+ unsigned i, blk_off, blk_num;
+
+ for (i=0; i<cnt; ++i) {
+ blk_num = (offset + i) >> 8;
+ blk_off = (offset + i) & 0xFF;
+
+ write_addr (blk_num);
+ write_byte (blk_off);
+ write_byte (*buffer++);
+ send_stop ();
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8xx.h>
+
+typedef volatile unsigned char vu_char;
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*-----------------------------------------------------------------------
+ * Protection Flags:
+ */
+#define FLAG_PROTECT_SET 0x01
+#define FLAG_PROTECT_CLEAR 0x02
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size (vu_long *addr, flash_info_t *info);
+
+int flash_write (uchar *, ulong, ulong);
+flash_info_t *addr2info (ulong);
+
+static int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+static int write_word (flash_info_t *info, ulong dest, ulong data);
+static void flash_get_offsets (ulong base, flash_info_t *info);
+static int flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init (void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE;
+ unsigned long size;
+ int i;
+
+ /* Init: enable write,
+ * or we cannot even write flash commands
+ */
+ bcsr->bd_ctrl |= BD_CTRL_FLWE;
+
+ for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+ flash_info[i].flash_id = FLASH_UNKNOWN;
+ }
+
+ /* Static FLASH Bank configuration here - FIXME XXX */
+
+ size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
+
+ if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+ printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
+ size, size<<20);
+ }
+
+ /* Remap FLASH according to real size */
+ memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+ memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |
+ (memctl->memc_br1 & ~(BR_BA_MSK));
+
+ /* Re-do sizing to get full correct info */
+ size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+
+ flash_info[0].size = size;
+
+ /* monitor protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+ &flash_info[0]);
+
+#ifdef CFG_FLASH_ENV_ADDR
+ /* ENV protection ON by default */
+ (void)flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_ENV_ADDR,
+ CFG_FLASH_ENV_ADDR+CFG_ENV_SIZE-1,
+ &flash_info[0]);
+#endif
+
+ return (size);
+}
+
+/*-----------------------------------------------------------------------
+ * Check or set protection status for monitor sectors
+ *
+ * The monitor always occupies the _first_ part of the _first_ Flash bank.
+ */
+static int flash_protect (int flag, ulong from, ulong to, flash_info_t *info)
+{
+ ulong b_end = info->start[0] + info->size - 1; /* bank end address */
+ int rc = 0;
+ int first = -1;
+ int last = -1;
+ int i;
+
+ if (to < info->start[0]) {
+ return (0);
+ }
+
+ for (i=0; i<info->sector_count; ++i) {
+ ulong end; /* last address in current sect */
+ short s_end;
+
+ s_end = info->sector_count - 1;
+
+ end = (i == s_end) ? b_end : info->start[i + 1] - 1;
+
+ if (from > end) {
+ continue;
+ }
+ if (to < info->start[i]) {
+ continue;
+ }
+
+ if (from == info->start[i]) {
+ first = i;
+ if (last < 0) {
+ last = s_end;
+ }
+ }
+ if (to == end) {
+ last = i;
+ if (first < 0) {
+ first = 0;
+ }
+ }
+ }
+
+ for (i=first; i<=last; ++i) {
+ if (flag & FLAG_PROTECT_CLEAR) {
+ info->protect[i] = 0;
+ } else if (flag & FLAG_PROTECT_SET) {
+ info->protect[i] = 1;
+ }
+ if (info->protect[i]) {
+ rc = 1;
+ }
+ }
+ return (rc);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets (ulong base, flash_info_t *info)
+{
+ int i;
+
+ /* set up sector start adress table */
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000);
+ }
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info (flash_info_t *info)
+{
+ int i;
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_INTEL: printf ("Intel "); break;
+ default: printf ("Unknown Vendor "); break;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
+ break;
+ default: printf ("Unknown Chip Type\n");
+ break;
+ }
+
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i=0; i<info->sector_count; ++i) {
+ if ((i % 5) == 0)
+ printf ("\n ");
+ printf (" %08lX%s",
+ info->start[i],
+ info->protect[i] ? " (RO)" : " "
+ );
+ }
+ printf ("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+{
+ short i;
+ ulong value;
+ ulong base = (ulong)addr;
+
+ /* Write "Intelligent Identifier" command: read Manufacturer ID */
+ *addr = 0x90909090;
+
+ value = addr[0];
+ switch (value) {
+ case (MT_MANUFACT & 0x00FF00FF): /* MT or => Intel */
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* no or unknown flash */
+ }
+
+ value = addr[1]; /* device ID */
+
+ switch (value) {
+ case (INTL_ID_28F016S):
+ info->flash_id += FLASH_28F016SV;
+ info->sector_count = 32;
+ info->size = 0x00400000;
+ break; /* => 2x2 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ return (0); /* => no or unknown flash */
+
+ }
+
+ /* set up sector start adress table */
+ for (i = 0; i < info->sector_count; i++) {
+ info->start[i] = base + (i * 0x00020000);
+ /* don't know how to check sector protection */
+ info->protect[i] = 0;
+ }
+
+ /*
+ * Prevent writes to uninitialized FLASH.
+ */
+ if (info->flash_id != FLASH_UNKNOWN) {
+ addr = (vu_long *)info->start[0];
+
+ *addr = 0xFFFFFF; /* reset bank to read array mode */
+ }
+
+ return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+void flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+ vu_long *addr;
+ int flag, prot, sect;
+ ulong start, now, last;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf ("- missing\n");
+ } else {
+ printf ("- no sectors to erase\n");
+ }
+ return;
+ }
+
+ if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL) {
+ printf ("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return;
+ }
+
+ prot = 0;
+ for (sect=s_first; sect<=s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf ("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf ("\n");
+ }
+
+ start = get_timer (0);
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect<=s_last; sect++) {
+ if (info->protect[sect] == 0) { /* not protected */
+ addr = (vu_long *)(info->start[sect]);
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Single Block Erase Command */
+ *addr = 0x20202020;
+ /* Confirm */
+ *addr = 0xD0D0D0D0;
+ /* Resume Command, as per errata update */
+ *addr = 0xD0D0D0D0;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 80us - let's wait 1 ms */
+ udelay (1000);
+
+ while ((*addr & 0x00800080) != 0x00800080) {
+ if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+ printf ("Timeout\n");
+ *addr = 0xFFFFFFFF; /* reset bank */
+ return;
+ }
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc ('.');
+ last = now;
+ }
+ }
+ }
+ }
+
+ /* reset to read mode */
+ *addr = 0xFFFFFFFF; /* reset bank */
+
+ printf (" done\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+flash_info_t *addr2info (ulong addr)
+{
+ flash_info_t *info;
+ int i;
+
+ for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
+ if ((addr >= info->start[0]) &&
+ (addr < (info->start[0] + info->size)) ) {
+ return (info);
+ }
+ }
+
+ return (NULL);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash.
+ * Make sure all target addresses are within Flash bounds,
+ * and no protected sectors are hit.
+ * Returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ * 4 - target range includes protected sectors
+ * 8 - target address not in Flash memory
+ */
+int flash_write (uchar *src, ulong addr, ulong cnt)
+{
+ int i;
+ ulong end = addr + cnt - 1;
+ flash_info_t *info_first = addr2info (addr);
+ flash_info_t *info_last = addr2info (end );
+ flash_info_t *info;
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ if (!info_first || !info_last) {
+ return (8);
+ }
+
+ for (info = info_first; info <= info_last; ++info) {
+ ulong b_end = info->start[0] + info->size; /* bank end addr */
+ short s_end = info->sector_count - 1;
+ for (i=0; i<info->sector_count; ++i) {
+ ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
+
+ if ((end >= info->start[i]) && (addr < e_addr) &&
+ (info->protect[i] != 0) ) {
+ return (4);
+ }
+ }
+ }
+
+ /* finally write data to flash */
+ for (info = info_first; info <= info_last && cnt>0; ++info) {
+ ulong len;
+
+ len = info->start[0] + info->size - addr;
+ if (len > cnt)
+ len = cnt;
+ if ((i = write_buff(info, src, addr, len)) != 0) {
+ return (i);
+ }
+ cnt -= len;
+ addr += len;
+ src += len;
+ }
+ return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+static int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+ ulong cp, wp, data;
+ int i, l, rc;
+
+ wp = (addr & ~3); /* get lower word aligned address */
+
+ /*
+ * handle unaligned start bytes
+ */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i=0, cp=wp; i<l; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+ for (; i<4 && cnt>0; ++i) {
+ data = (data << 8) | *src++;
+ --cnt;
+ ++cp;
+ }
+ for (; cnt==0 && i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ }
+
+ /*
+ * handle word aligned part
+ */
+ while (cnt >= 4) {
+ data = 0;
+ for (i=0; i<4; ++i) {
+ data = (data << 8) | *src++;
+ }
+ if ((rc = write_word(info, wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 4;
+ cnt -= 4;
+ }
+
+ if (cnt == 0) {
+ return (0);
+ }
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
+ data = (data << 8) | *src++;
+ --cnt;
+ }
+ for (; i<4; ++i, ++cp) {
+ data = (data << 8) | (*(uchar *)cp);
+ }
+
+ return (write_word(info, wp, data));
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word (flash_info_t *info, ulong dest, ulong data)
+{
+ vu_long *addr = (vu_long *)dest;
+ ulong start, csr;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*addr & data) != data) {
+ return (2);
+ }
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ /* Write Command */
+ *addr = 0x10101010;
+
+ /* Write Data */
+ *addr = data;
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* data polling for D7 */
+ start = get_timer (0);
+ flag = 0;
+ while (((csr = *addr) & 0x00800080) != 0x00800080) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ flag = 1;
+ break;
+ }
+ }
+ if (csr & 0x00400040) {
+printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
+ flag = 1;
+ }
+
+ /* Clear Status Registers Command */
+ *addr = 0x50505050;
+ /* Reset to read array mode */
+ *addr = 0xFFFFFFFF;
+
+ return (flag);
+}
+
+/*-----------------------------------------------------------------------
+ */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <commproc.h>
+#include "mpc8xx.h"
+
+/* ------------------------------------------------------------------------- */
+
+static long int dram_size (long int, long int *, long int);
+
+/* ------------------------------------------------------------------------- */
+
+#define _NOT_USED_ 0xFFFFFFFF
+
+const uint sdram_table[] =
+{
+ /*
+ * Single Read. (Offset 0 in UPMA RAM)
+ */
+ 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
+ 0x1ff77c47, /* last */
+ /*
+ * SDRAM Initialization (offset 5 in UPMA RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0x1ff77c34, 0xefeabc34, 0x1fb57c35, /* last */
+ /*
+ * Burst Read. (Offset 8 in UPMA RAM)
+ */
+ 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
+ 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPMA RAM)
+ */
+ 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPMA RAM)
+ */
+ 0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
+ 0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPMA RAM)
+ */
+ 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
+ 0xfffffc84, 0xfffffc07, /* last */
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPMA RAM)
+ */
+ 0x7ffffc07, /* last */
+ _NOT_USED_, _NOT_USED_, _NOT_USED_,
+};
+
+/* ------------------------------------------------------------------------- */
+
+
+/*
+ * Check Board Identity:
+ *
+ * Test ID string (IP860...)
+ *
+ * Always return 1 for "L" type (no second SDRAM bank)
+ */
+
+int checkboard (void)
+{
+ unsigned char *s, *e;
+ unsigned char buf[64];
+ int i;
+
+ i = getenv_r("serial#", buf, sizeof(buf));
+ s = (i>0) ? buf : NULL;
+
+ if (!s || strncmp(s, "IP860", 5)) {
+ puts ("### No HW ID - assuming IP860");
+ } else {
+ for (e=s; *e; ++e) {
+ if (*e == ' ')
+ break;
+ }
+
+ for ( ; s<e; ++s) {
+ putc (*s);
+ }
+ }
+
+ putc ('\n');
+
+ return (1);
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram (int board_type)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ long int size;
+
+ upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
+
+ /*
+ * Preliminary prescaler for refresh
+ */
+ memctl->memc_mptpr = 0x0400;
+
+ memctl->memc_mar = 0x00000088;
+
+ /*
+ * Map controller banks 2 to the SDRAM address
+ */
+ memctl->memc_or2 = CFG_OR2;
+ memctl->memc_br2 = CFG_BR2;
+
+ /* IP860 boards have only one bank SDRAM */
+
+
+ udelay(200);
+
+ /* perform SDRAM initializsation sequence */
+
+ memctl->memc_mamr = 0xC3804114;
+ memctl->memc_mcr = 0x80004105; /* run precharge pattern from loc 5 */
+ udelay(1);
+ memctl->memc_mamr = 0xC3804118;
+ memctl->memc_mcr = 0x80004130; /* run refresh pattern 8 times */
+
+ udelay (1000);
+
+ /*
+ * Check SDRAM Memory Size
+ */
+ size = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE, SDRAM_MAX_SIZE);
+
+ udelay (1000);
+
+ memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
+ memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+
+ udelay(10000);
+
+ /*
+ * Also, map other memory to correct position
+ */
+
+#if (defined(CFG_OR1) && defined(CFG_BR1_PRELIM))
+ memctl->memc_or1 = CFG_OR1;
+ memctl->memc_br1 = CFG_BR1;
+#endif
+
+#if defined(CFG_OR3) && defined(CFG_BR3)
+ memctl->memc_or3 = CFG_OR3;
+ memctl->memc_br3 = CFG_BR3;
+#endif
+
+#if defined(CFG_OR4) && defined(CFG_BR4)
+ memctl->memc_or4 = CFG_OR4;
+ memctl->memc_br4 = CFG_BR4;
+#endif
+
+#if defined(CFG_OR5) && defined(CFG_BR5)
+ memctl->memc_or5 = CFG_OR5;
+ memctl->memc_br5 = CFG_BR5;
+#endif
+
+#if defined(CFG_OR6) && defined(CFG_BR6)
+ memctl->memc_or6 = CFG_OR6;
+ memctl->memc_br6 = CFG_BR6;
+#endif
+
+#if defined(CFG_OR7) && defined(CFG_BR7)
+ memctl->memc_or7 = CFG_OR7;
+ memctl->memc_br7 = CFG_BR7;
+#endif
+
+ return (size);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'. Some (not all) hardware errors are detected:
+ * - short between address lines
+ * - short between data lines
+ */
+
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile memctl8xx_t *memctl = &immap->im_memctl;
+ volatile long int *addr;
+ long int cnt, val;
+
+ memctl->memc_mamr = mamr_value;
+
+ for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ *addr = ~cnt;
+ }
+
+ /* write 0 to base address */
+ addr = base;
+ *addr = 0;
+
+ /* check at base address */
+ if ((val = *addr) != 0) {
+ return (0);
+ }
+
+ for (cnt = 1; ; cnt <<= 1) {
+ addr = base + cnt; /* pointer arith! */
+
+ val = *addr;
+
+ if (val != (~cnt)) {
+ return (cnt * sizeof(long));
+ }
+ }
+ /* NOTREACHED */
+}
+
+/* ------------------------------------------------------------------------- */
+
+void reset_phy(void)
+{
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ ulong mask = PB_ENET_RESET | PB_ENET_JABD;
+ ulong reg;
+
+ /* Make sure PHY is not in low-power mode */
+ immr->im_cpm.cp_pbpar &= ~(mask); /* GPIO */
+ immr->im_cpm.cp_pbodr &= ~(mask); /* active output */
+
+ /* Set JABD low (no JABber Disable),
+ * and RESET high (Reset PHY)
+ */
+ reg = immr->im_cpm.cp_pbdat;
+ reg = (reg & ~PB_ENET_JABD) | PB_ENET_RESET;
+ immr->im_cpm.cp_pbdat = reg;
+
+ /* now drive outputs */
+ immr->im_cpm.cp_pbdir |= mask ; /* output */
+ udelay(1000);
+ /*
+ * Release RESET signal
+ */
+ immr->im_cpm.cp_pbdat &= ~(PB_ENET_RESET);
+ udelay (1000);
+}
+
+/* ------------------------------------------------------------------------- */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ common/dlmalloc.o (.text)
+ ppc/ppcstring.o (.text)
+ cpu/mpc8xx/interrupts.o (.text)
+ ppc/time.o (.text)
+ ppc/ticks.o (.text)
+/**
+ . = env_offset;
+ common/environment.o(.text)
+**/
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ /* WARNING - the following is hand-optimized to fit within */
+ /* the sector layout of our flash chips! XXX FIXME XXX */
+
+ cpu/mpc8xx/start.o (.text)
+ ppc/ppcstring.o (.text)
+ cpu/mpc8xx/interrupts.o (.text)
+ ppc/time.o (.text)
+ ppc/ticks.o (.text)
+/**
+ . = env_offset;
+ common/environment.o(.text)
+**/
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ }
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.rodata)
+ *(.rodata1)
+ }
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x0FFF) & 0xFFFFF000;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(4096);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(4096);
+ __init_end = .;
+
+ __bss_start = .;
+ .bss :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ }
+ _end = . ;
+ PROVIDE (end = .);
+}
+
/* ENV protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CFG_FLASH_ENV_ADDR,
- CFG_FLASH_ENV_ADDR+CFG_FLASH_ENV_SIZE-1,
+ CFG_FLASH_ENV_ADDR+CFG_ENV_SIZE-1,
&flash_info[0]);
#endif
.plt : { *(.plt) }
.text :
{
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/environment.o(.text)
*(.text)
*(.fixup)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
.plt : { *(.plt) }
.text :
{
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
*(.text)
*(.fixup)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
PROVIDE(_f_init_rom = .);
.init : {
- mpc8240/start.o (.text)
+ cpu/mpc8240/start.o (.text)
*(.init)
} > ram
_init_size = SIZEOF(.init);
PROVIDE(_f_init_rom = .);
.init : {
- mpc8240/start.o (.text)
+ cpu/mpc8240/start.o (.text)
*(.init)
} > ram
_init_size = SIZEOF(.init);
.plt : { *(.plt) }
.text :
{
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/environment.o(.text)
*(.text)
*(.fixup)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/ppcstring.o (.text)
ppc/vsprintf.o (.text)
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- mpc8xx/start.o (.text)
+ cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
ppc/vsprintf.o (.text)
ppc/crc32.o (.text)
endif
COBJS = board.o main.o command.o \
cmd_boot.o cmd_bootm.o cmd_cache.o \
- cmd_console.o cmd_flash.o cmd_ide.o \
- cmd_mem.o cmd_net.o cmd_nvedit.o \
- s_record.o dlmalloc.o kgdb.o \
- console.o lists.o devices.o
+ cmd_console.o cmd_eeprom.o cmd_flash.o \
+ cmd_ide.o cmd_mem.o cmd_net.o \
+ cmd_nvedit.o s_record.o dlmalloc.o \
+ kgdb.o console.o lists.o devices.o
OBJS = $(AOBJS) $(COBJS)
static char *failed = "*** failed ***\n";
+
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# if (CFG_ENV_ADDR >= CFG_FLASH_BASE) && \
+ (CFG_ENV_ADDR+CFG_ENV_SIZE) < (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+# define ENV_IS_EMBEDDED
+# endif
+#endif /* CFG_ENV_IS_IN_FLASH */
+#if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_FLASH_BASE) || \
+ (CFG_ENV_ADDR >= (CFG_FLASH_BASE + CFG_MONITOR_LEN)) ) || \
+ defined(CFG_ENV_IS_IN_NVRAM)
+#define TOTAL_MALLOC_LEN (CFG_MALLOC_LEN + CFG_ENV_SIZE)
+#else
+#define TOTAL_MALLOC_LEN CFG_MALLOC_LEN
+#endif
+
/*
* Begin and End of memory area for malloc(), and current "brk"
*/
*/
static void mem_malloc_init (ulong dest_addr)
{
- mem_malloc_end = dest_addr;
- mem_malloc_start = dest_addr - CFG_MALLOC_LEN;
- mem_malloc_brk = mem_malloc_start;
+ mem_malloc_end = dest_addr;
+ mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN;
+ mem_malloc_brk = mem_malloc_start;
memset ((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start);
}
int board_type;
ulong addr_moni, addr_sp;
ulong dram_size;
+ int i, baudrate;
char *s, *e;
- int baudrate;
+ uchar tmp[64]; /* long enough for environment variables */
/* Pointer to initial global data area */
init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
#endif /* CONFIG_8260 */
- s = getenv ("baudrate");
- baudrate = s ? (int)simple_strtoul(s, NULL, 10) : CONFIG_BAUDRATE;
+ /*
+ * we need the timebase for udelay() in DRAM setup,
+ * and in case we need to read the environment from EEPROM
+ */
+ init_timebase ();
+
+ idata->env_addr = env_init();
+
+ i = getenv_r ("baudrate", tmp, sizeof(tmp));
+ baudrate = (i > 0) ? (int)simple_strtoul(tmp, NULL, 10) : CONFIG_BAUDRATE;
/* set up serial port */
serial_init (idata->cpu_clk, baudrate);
}
#endif
- /* we need the timebase for udelay() in DRAM setup */
- init_timebase ();
-
printf (" DRAM: ");
if ((dram_size = initdram (board_type)) > 0) {
addr_moni = CFG_SDRAM_BASE + dram_size - len;
#ifdef DEBUG
- printf (" Relocating to: %08lx\n", addr_moni);
+ printf (" Relocating to: %08lx, %d bytes for malloc()\n",
+ addr_moni, TOTAL_MALLOC_LEN);
#endif
/*
*
* We leave room for the malloc() arena.
*/
- bd = (bd_t *)(addr_moni - sizeof(bd_t) - CFG_MALLOC_LEN);
+ len = sizeof(bd_t) + TOTAL_MALLOC_LEN;
+
+ bd = (bd_t *)(addr_moni - len);
#ifdef DEBUG
printf (" Board Info at: %08lx\n", (ulong)bd);
addr_sp = (ulong)bd - 128;
addr_sp &= ~0xF;
-#if defined(CFG_FLASH_ENV_BUF)
- /*
- * Unfortunately, some boards (like the Cogent CMA302 flash I/O
- * Module) have ridiculously large sectors (512KB) because they
- * have 8 x 8 bit wide flash chips arranged so that each chip has
- * one of the byte lanes in a 64 bit word. Not only that, the
- * Intel 28F008S5 flash chips have 64K sectors (16 of them, for
- * 1Mbyte each). So effectively, the CMA302 has 16 x 512KB
- * sectors. We need some space to store the data when programming
- * one of these flash sectors, so the only way I can think of at
- * the moment is to allocate it here, between the board data and
- * the top of the stack.
- */
- addr_sp -= CFG_FLASH_ENV_BUF;
-#endif /* CFG_FLASH_ENV_BUF */
-
/*
* Save local variables to board info struct
*/
/* IP Address */
bd->bi_ip_addr = 0;
- s = getenv ("ipaddr");
+ i = getenv_r ("ipaddr", tmp, sizeof(tmp));
+ s = (i > 0) ? tmp : NULL;
for (reg=0; reg<4; ++reg) {
ulong val = s ? simple_strtoul(s, &e, 10) : 0;
bd->bi_ip_addr <<= 8;
s = (*e) ? e+1 : e;
}
- s = getenv ("ethaddr");
+ i = getenv_r ("ethaddr", tmp, sizeof(tmp));
+ s = (i > 0) ? tmp : NULL;
#ifdef CONFIG_MBX
if (s == NULL)
if (s)
s = (*e) ? e+1 : e;
}
+#ifdef CONFIG_HERMES
+ if ((board_type >> 16) == 2)
+ bd->bi_ethspeed = board_type & 0xFFFF;
+ else
+ bd->bi_ethspeed = 0xFFFF;
+#endif
#if defined(CFG_CLKS_IN_HZ)
bd->bi_intfreq = idata->cpu_clk; /* Internal Freq, in Hz */
init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
extern void malloc_bin_reloc (ulong);
-#if defined(CONFIG_SPD823TS) || defined(CONFIG_IVMS8)
- void reset_phy(void);
-#endif
#ifdef DEBUG
printf(" Now running in RAM - dest_addr = 0x%08lx\n", dest_addr);
#endif
}
+#if defined(CONFIG_IP860)
+ icache_enable(); /* it's time to enable the instruction cache */
+#endif
+
asm ("sync ; isync");
/*
}
bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
-#if defined(CFG_FLASH_ENV_ADDR)
- /*
- * Protect the sector that the environment is in.
- *
- * This scheme (i.e. bi_flashoffset in the board info) cannot
- * really reflect an arbitrarily placed environment flash sector,
- * but lets just do our best, and assume that if CFG_FLASH_ENV_ADDR
- * is defined it will be in a sensible location e.g. either the
- * first sector, or the sector just after the monitor, if it is
- * in flash.
- */
- {
- ulong addr, newoff;
- flash_info_t *fip;
- int i, j;
-
- /* address of last byte in the environment */
- addr = CFG_FLASH_ENV_ADDR + CFG_FLASH_ENV_SIZE - 1;
-
- /* make sure it is within the flash */
- if ((fip = addr2info(addr)) == NULL)
- panic("environment address 0x%08lx is not within flash!\n", addr);
-
- /* move it to the sector boundary */
- for (i = 0, j = 1; j < fip->sector_count; i++, j++)
- if (addr >= fip->start[i] && addr < fip->start[j])
- break;
- if (j == fip->sector_count)
- addr = fip->start[0] + fip->size;
- else
- addr = fip->start[j];
-
- /* adjust flashoffset if required */
- newoff = addr - bd->bi_flashstart;
- if (bd->bi_flashoffset < newoff)
- bd->bi_flashoffset = newoff;
- }
-#endif
-
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r (bd);
+ bd->bi_mon_fnc->malloc = malloc;
+ bd->bi_mon_fnc->free = free;
+
+ /* initialize malloc() area */
+ mem_malloc_init (dest_addr);
+ malloc_bin_reloc (reloc_off);
+
+ /* relocate environment function pointers etc. */
+ env_relocate (reloc_off);
+
#ifdef CONFIG_COGENT
/* miscellaneous platform dependent initialisations */
misc_init_r(bd);
#endif
-#if defined(CONFIG_SPD823TS) || defined(CONFIG_IVMS8)
+#ifdef CONFIG_HERMES
+ if (bd->bi_ethspeed != 0xFFFF)
+ hermes_start_lxt980((int)bd->bi_ethspeed);
+#endif
+
+#if defined(CONFIG_SPD823TS) || \
+ defined(CONFIG_IVMS8) || \
+ defined(CONFIG_IP860)
# ifdef DEBUG
- printf("Reset Ethernet PHY\n");
+ printf(" Reset Ethernet PHY\n");
# endif
reset_phy ();
#endif
#endif
#ifdef DEBUG
- printf("Monitor relocated to 0x%08lx\n", dest_addr);
+ printf(" Monitor relocated to 0x%08lx\n", dest_addr);
#endif
/*
pci_init();
#endif
- bd->bi_mon_fnc->malloc = malloc;
- bd->bi_mon_fnc->free = free;
-
- /* initialize malloc() area */
- mem_malloc_init (dest_addr);
- malloc_bin_reloc (reloc_off);
-
/** LEAVE THIS HERE **/
/* Initialize devices */
devices_init();
/* Initialize the console (after the relocation and devices init) */
- console_init_r ();
+ console_init_r (reloc_off);
putc('\n');
/**********************/
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
}
+#ifdef CONFIG_HERMES
+ printf (" ethspeed = %6d MHz\n", bd->bi_ethspeed);
+#endif
printf ("\n IP addr =");
for (i=0; i<4; ++i) {
printf ("%c%ld", i ? '.' : ' ', (ip >> 24) & 0xFF);
addr = simple_strtoul(argv[1], NULL, 16);
}
+#ifdef CONFIG_HERMES
+ hermes_set_led (1);
+#endif
printf ("## Booting Linux kernel at %08lx ...\n", addr);
/* Copy header so we can blank CRC field for re-calculation */
printf ("Bad Magic Number\n");
return;
}
+#ifdef CONFIG_HERMES
+ hermes_set_led (2);
+#endif
data = (ulong)&header;
len = sizeof(image_header_t);
printf ("Bad Header Checksum\n");
return;
}
+#ifdef CONFIG_HERMES
+ hermes_set_led (3);
+#endif
/* for multi-file images we need the data part, too */
print_image_hdr ((image_header_t *)addr);
}
printf ("OK\n");
}
+#ifdef CONFIG_HERMES
+ hermes_set_led (4);
+#endif
len_ptr = (ulong *)data;
printf ("Unsupported Architecture\n");
return;
}
+#ifdef CONFIG_HERMES
+ hermes_set_led (5);
+#endif
switch (hdr->ih_type) {
case IH_TYPE_STANDALONE: name = "Standalone Application";
default: printf ("Wrong Image Type for %s command\n", cmdtp->name);
return;
}
+#ifdef CONFIG_HERMES
+ hermes_set_led (6);
+#endif
/*
* We have reached the point of no return: we are going to
return;
}
printf ("OK\n");
+#ifdef CONFIG_HERMES
+ hermes_set_led (7);
+#endif
switch (hdr->ih_type) {
case IH_TYPE_STANDALONE:
printf ("Can't boot image type %d\n", hdr->ih_type);
return;
}
+#ifdef CONFIG_HERMES
+ hermes_set_led (8);
+#endif
/*
* Booting a (Linux) kernel image
* Check if there is an initrd image
*/
if (argc >= 3) {
+#ifdef CONFIG_HERMES
+ hermes_set_led (9);
+#endif
addr = simple_strtoul(argv[2], NULL, 16);
printf ("## Loading RAMDisk Image at %08lx ...\n", addr);
do_reset (cmdtp, bd, flag, argc, argv);
}
+#ifdef CONFIG_HERMES
+ hermes_set_led (10);
+#endif
print_image_hdr (hdr);
data = addr + sizeof(image_header_t);
}
printf ("OK\n");
}
+#ifdef CONFIG_HERMES
+ hermes_set_led (11);
+#endif
if ((hdr->ih_os != IH_OS_LINUX) ||
(hdr->ih_arch != IH_CPU_PPC) ||
if (nsp >= sp)
initrd_start = nsp;
}
+#ifdef CONFIG_HERMES
+ hermes_set_led (12);
+#endif
initrd_end = initrd_start + hdr->ih_size;
printf (" Loading Ramdisk to %08lx, end %08lx ... ",
u_long i_start = data + len_ptr[0];
u_long tail = len_ptr[0] % 4;
+#ifdef CONFIG_HERMES
+ hermes_set_led (13);
+#endif
if (tail) {
i_start += 4 - tail;
}
/*
* no initrd image
*/
+#ifdef CONFIG_HERMES
+ hermes_set_led (14);
+#endif
initrd_start = 0;
initrd_end = 0;
}
printf ("## Transferring control to Linux (at address %08lx) ...\n",
(ulong)kernel);
#endif
+#ifdef CONFIG_HERMES
+ hermes_set_led (15);
+#endif
/*
* Linux Kernel Parameters:
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <mpc8xx_irq.h>
+#include <ppcboot.h>
+#include <config.h>
+#include <command.h>
+#include <mpc8xx.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
+
+extern void eeprom_init (void);
+extern void eeprom_read (unsigned offset, uchar *buffer, unsigned cnt);
+extern void eeprom_write (unsigned offset, uchar *buffer, unsigned cnt);
+
+/* ------------------------------------------------------------------------- */
+
+void do_eeprom (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ switch (argc) {
+ default:
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return;
+ case 5:
+ /* 4 args */
+
+ if (strcmp(argv[1],"read") == 0) {
+ ulong addr = simple_strtoul(argv[2], NULL, 16);
+ ulong off = simple_strtoul(argv[3], NULL, 16);
+ ulong cnt = simple_strtoul(argv[4], NULL, 16);
+
+ printf ("\nEEPROM read: addr %08lx off %04lx count %ld ... ",
+ addr, off, cnt);
+
+ eeprom_init ();
+ eeprom_read (off, (uchar *)addr, cnt);
+
+ printf ("done\n");
+ return;
+
+ } else if (strcmp(argv[1],"write") == 0) {
+ ulong addr = simple_strtoul(argv[2], NULL, 16);
+ ulong off = simple_strtoul(argv[3], NULL, 16);
+ ulong cnt = simple_strtoul(argv[4], NULL, 16);
+
+ printf ("\nEEPROM write: addr %08lx off %04lx count %ld ... ",
+ addr, off, cnt);
+
+ eeprom_init ();
+ eeprom_write(off, (uchar *)addr, cnt);
+
+ printf ("done\n");
+ printf ("done\n");
+ return;
+ } else {
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ }
+
+ return;
+ }
+}
+
+#endif /* CFG_CMD_EEPROM */
extern flash_info_t flash_info[]; /* info for FLASH chips */
-void flash_sect_erase (ulong addr_first, ulong addr_last);
-void flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
-
/*
* The user interface starts numbering for Flash banks with 1
* for historical reasons.
#include <ppcboot.h>
#include <command.h>
#include <cmd_nvedit.h>
-#ifdef CONFIG_4xx
-#include <malloc.h>
-#endif
+#include <linux/stddef.h>
-/*
+/************************************************************************
+ *
* The environment storages is simply a list of '\0'-terminated
* "name=value" strings, the end of the list marked by a double '\0'.
- * New entries are always addrd at the end. Deleting an entry shifts
+ * New entries are always added at the end. Deleting an entry shifts
* the remaining entries to the front. Replacing an entry is a
* combination of deleting the old and adding the new value.
+ *
+ * The environment is preceeded by a 32 bit CRC over the data part.
+ *
+ ************************************************************************
*/
-#ifdef CONFIG_NVRAM_ENV
-uchar *environment = (uchar *)CFG_NVRAM_VAR_ADDR;
-ulong env_size = CFG_NVRAM_ENV_SIZE;
-#else
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# if (CFG_ENV_ADDR >= CFG_FLASH_BASE) && \
+ (CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+# define ENV_IS_EMBEDDED
+# endif
+#endif /* CFG_ENV_IS_IN_FLASH */
-#if defined(CFG_FLASH_ENV_ADDR)
-static uchar environment[CFG_FLASH_ENV_SIZE];
-static ulong env_size = CFG_FLASH_ENV_SIZE;
+#define ENV_SIZE (CFG_ENV_SIZE - sizeof(long))
-/* need both ENV and flash */
-#if ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
-static uchar *flash_addr = (uchar *)CFG_FLASH_ENV_ADDR;
-#endif /* ENV, FLASH */
+#if !defined(ENV_IS_EMBEDDED)
+#include <malloc.h>
+#endif
-/*
- * the contents of the rom_addr pointer will not change when the monitor
- * is relocated into RAM and so will contain the old address of the
- * environment[] array in flash, but the environment[] array itself *will*
- * be relocated. Hence, we can tell whether the monitor has been relocated
- * by comparing the value of rom_addr with environment.
- */
-static uchar *rom_addr = environment;
-#if defined(CONFIG_COGENT) && !defined(CONFIG_CMA302)
-#define ISVALID(p) 0 /* can't get motherboard flash working yet */
-#else
-#define ISVALID(p) (crc32(0, (char *)(p), env_size - sizeof (ulong)) == \
- *(ulong *)((char *)(p) + env_size - sizeof (ulong)))
-#endif
-#define MAKEVALID(p, s) (*(ulong *)((char *)(p) + (s) - sizeof (ulong)) = \
- crc32(0, (char *)(p), (s) - sizeof (ulong)))
+typedef struct environment_s {
+ ulong crc; /* CRC32 over data bytes */
+ uchar data[ENV_SIZE];
+} env_t;
+
+/*--- NVRAM ----------------------------------------------------------*/
+#ifdef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
+
+static env_t *env_ptr = (env_t *)CFG_ENV_ADDR;
+
+/*--- EEPROM ----------------------------------------------------------*/
+#elif defined(CFG_ENV_IS_IN_EEPROM) /* Environment is in EEPROM */
+static env_t *env_ptr = NULL;
+
+/*--- FLASH ----------------------------------------------------------*/
+#elif defined(CFG_ENV_IS_IN_FLASH) /* Environment is in Flash */
+
+# if defined(ENV_IS_EMBEDDED) /* embedded within PPCBoot */
-#else /* CFG_FLASH_ENV_ADDR */
extern uchar environment[];
-extern ulong env_size;
+static env_t *env_ptr = (env_t *)(&environment[0]);
+# if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
+static uchar *flash_addr = &environment[0];
+# endif /* ENV, FLASH */
+# else /* !ENV_IS_EMBEDDED*/ /* not embedded within PPCBoot */
+static env_t *env_ptr = (env_t *)CFG_ENV_ADDR;
/* need both ENV and flash */
-#if ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
-static uchar *flash_addr = environment;
-#endif /* ENV, FLASH */
-#endif /* CFG_FLASH_ENV_ADDR */
-#endif /* CONFIG_NVRAM_ENV */
-
-static uchar *envmatch (uchar *, uchar *);
-#if defined(CFG_FLASH_ENV_ADDR)
-static uchar *env_init(void);
-#else
-static void env_init(void);
-#endif /* CFG_FLASH_ENV_ADDR */
+# if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
+static uchar *flash_addr = (uchar *)CFG_ENV_ADDR;
+# endif /* ENV, FLASH */
+# endif /* ENV_IS_EMBEDDED */
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+/*----------------------------------------------------------------------*/
+
+/************************************************************************
+ * Default settings to be used when no valid environment is found
+ */
#define XMK_STR(x) #x
#define MK_STR(x) XMK_STR(x)
"\0"
};
-char *getenv (uchar *name)
-{
- uchar *env, *nxt;
-#if defined(CFG_FLASH_ENV_ADDR)
- uchar *environment = env_init();
+/************************************************************************
+************************************************************************/
+
+static int envmatch (uchar *, int);
+
+/************************************************************************
+************************************************************************/
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+static uchar get_env_char_eeprom(int);
+#endif
+static uchar get_env_char_memory(int);
+static uchar *get_env_addr_memory(int);
+
+/* Function that returns a character from the environment */
+static uchar (*get_env_char)(int) =
+#ifdef CFG_ENV_IS_IN_EEPROM
+ get_env_char_eeprom;
#else
- env_init();
-#endif /* CFG_FLASH_ENV_ADDR */
+ get_env_char_memory;
+#endif
+/* Function that returns a pointer to a value from the environment */
+/* (Only memory version supported / needed). */
+static uchar *(*get_env_addr)(int) = get_env_addr_memory;
- for (env=environment; *env; env=nxt+1) {
- char *val;
+/************************************************************************
+************************************************************************/
- for (nxt=env; *nxt; ++nxt)
- ;
- val=envmatch(name, env);
- if (!val)
- continue;
- return (val);
+void env_relocate (ulong offset)
+{
+ init_data_t *idata = (init_data_t*)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
+#ifndef CFG_ENV_IS_IN_EEPROM
+ uchar *datap = (uchar *)(idata->env_addr + offset);
+#endif
+
+#if !defined(ENV_IS_EMBEDDED) || defined(CFG_ENV_IS_IN_NVRAM)
+ /*
+ * We must allocate a buffer for the environment
+ * (We _could_ work directly in NVRAM, however we want
+ * to modify persistent values only using "saveenv",
+ * so we need a RAM copy here, too.
+ */
+ env_ptr = (env_t *)malloc (CFG_ENV_SIZE);
+#else /* ENV_IS_EMBEDDED */
+ /*
+ * The environment buffer is embedded with the text segment,
+ * just relocate the environment pointer
+ */
+ env_ptr = (env_t *)((ulong)env_ptr + offset);
+#endif
+
+ /*
+ * Update all function pointers
+ * After relocation to RAM, we can always use the "memory" functions
+ */
+ get_env_char = get_env_char_memory;
+ get_env_addr = get_env_addr_memory;
+
+ if (
+#ifdef CFG_ENV_IS_IN_EEPROM
+ idata->env_addr == 0
+#else
+ datap == &default_environment[0]
+#endif
+ ) {
+ /*
+ * We should check here that the default environment
+ * does not overflow the buffer.
+ */
+ printf ("*** Warning - bad CRC, using default environment\n\n");
+ memset (env_ptr, 0, sizeof(env_t));
+ memcpy (env_ptr->data,
+ default_environment,
+ sizeof(default_environment));
}
+#if !defined(ENV_IS_EMBEDDED)
+ else {
+# if defined(CFG_ENV_IS_IN_NVRAM)
+ memcpy (env_ptr->data,
+ ((env_t *)CFG_ENV_ADDR)->data,
+ ENV_SIZE);
+# elif defined(CFG_ENV_IS_IN_EEPROM)
+ eeprom_read (offsetof(env_t,data), env_ptr->data, ENV_SIZE);
+# endif
+ }
+#endif
+ idata->env_addr = (ulong)&(env_ptr->data);
+}
+/************************************************************************
+************************************************************************/
- return (NULL);
+/*
+ * Utility function when we can read directly from memory
+ */
+static uchar get_env_char_memory (int index)
+{
+ init_data_t *idata = (init_data_t*)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
+ uchar *datap = (uchar *)idata->env_addr;
+
+ return (datap[index]);
}
-void do_printenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+
+static uchar *get_env_addr_memory(int index)
{
- uchar *env, *nxt;
- int i;
+ init_data_t *idata = (init_data_t*)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
+ uchar *datap = (uchar *)idata->env_addr;
-#if defined(CFG_FLASH_ENV_ADDR)
- uchar *environment = env_init();
-#else
- env_init();
-#endif /* CFG_FLASH_ENV_ADDR */
+ return (&datap[index]);
+}
+
+#ifdef CFG_ENV_IS_IN_EEPROM
+/*
+ * Utility function when we have to read from serial device
+ */
+static uchar get_env_char_eeprom (int index)
+{
+ uchar c;
+ eeprom_read (index, &c, 1);
+ return (c);
+}
+#endif /* CFG_ENV_IS_IN_EEPROM */
+
+/************************************************************************
+ * Command interface: print one or all environment variables
+ */
+
+void do_printenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ int i, k, nxt;
if (argc == 1) { /* Print all env variables */
- uchar *start = environment;
- for (env=environment; *env; env=nxt+1) {
- for (nxt=env; *nxt; ++nxt)
+ for (i=0; get_env_char(i) != '\0'; i=nxt+1) {
+ for (nxt=i; get_env_char(nxt) != '\0'; ++nxt)
;
- puts (env);
+ for (k=i; k<nxt; ++k)
+ putc(get_env_char(k));
putc ('\n');
if (tstc()) {
}
}
- printf("\nEnvironment size: %d bytes\n", env-start);
+ printf("\nEnvironment size: %d/%d bytes\n", i, ENV_SIZE);
return;
}
for (i=1; i<argc; ++i) { /* print single env variables */
char *name = argv[i];
- char *val = NULL;
- for (env=environment; *env; env=nxt+1) {
+ k = -1;
- for (nxt=env; *nxt; ++nxt)
+ for (i=0; get_env_char(i) != '\0'; i=nxt+1) {
+
+ for (nxt=i; get_env_char(nxt) != '\0'; ++nxt)
;
- val=envmatch(name, env);
- if (val) {
- puts (name);
- putc ('=');
- puts (val);
- putc ('\n');
- break;
+ k = envmatch(name, i);
+ if (k < 0) {
+ continue;
}
+ puts (name);
+ putc ('=');
+ while (k < nxt)
+ putc(get_env_char(k));
+ putc ('\n');
+ break;
}
- if (!val)
+ if (k < 0)
printf ("## Error: \"%s\" not defined\n", name);
}
}
+/************************************************************************
+ * Set a new environment variable,
+ * or replace or delete an existing one.
+ *
+ * This function will ONLY work with a in-RAM copy of the environment
+ */
+
void _do_setenv (bd_t *bd, int flag, int argc, char *argv[])
{
- int i, len;
+ int i, len, oldval;
int console = -1;
uchar *env, *nxt;
- uchar *oldval = NULL;
uchar *name;
-#if defined(CFG_FLASH_ENV_ADDR)
- uchar *environment = env_init();
- ulong real_env_size = env_size;
- ulong env_size = real_env_size - sizeof (ulong);
-#else
- env_init();
-#endif /* CFG_FLASH_ENV_ADDR */
+ uchar *env_data = get_env_addr(0);
+
+ if (!env_data) /* need copy in RAM */
+ return;
name = argv[1];
/*
* search if variable with this name already exists
*/
- for (env=environment; *env; env=nxt+1) {
+ oldval = -1;
+ for (env=env_data; *env; env=nxt+1) {
for (nxt=env; *nxt; ++nxt)
;
- if ((oldval=envmatch(name, env)) != NULL)
+ if ((oldval = envmatch(name, env-env_data)) >= 0)
break;
}
/*
* Delete any existing definition
*/
- if (oldval) {
+ if (oldval >= 0) {
#ifndef CONFIG_ENV_OVERWRITE
/*
* Ethernet Address and serial# can be set only once
*++env = '\0';
}
-#if defined(CFG_FLASH_ENV_ADDR)
- MAKEVALID(environment, real_env_size);
-#endif /* CFG_FLASH_ENV_ADDR */
-
/* Delete only ? */
- if (argc < 3)
+ if (argc < 3) {
+ /* Update CRC */
+ env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
+
return;
+ }
/*
* Append new definition at the end
*/
- for (env=environment; *env || *(env+1); ++env)
+ for (env=env_data; *env || *(env+1); ++env)
;
- if (env > environment)
+ if (env > env_data)
++env;
/*
* Overflow when:
- * "name" + "=" + "val" +"\0\0" > env_size - (env-environment)
+ * "name" + "=" + "val" +"\0\0" > ENV_SIZE - (env-env_data)
*/
len = strlen(name) + 2;
/* add '=' for first arg, ' ' for all others */
for (i=2; i<argc; ++i) {
len += strlen(argv[i]) + 1;
}
- if (len > (&environment[env_size]-env)) {
+ if (len > (&env_data[ENV_SIZE]-env)) {
printf ("## Error: environment overflow, \"%s\" deleted\n", name);
return;
}
/* end is marked with double '\0' */
*++env = '\0';
-#ifdef CONFIG_NVRAM_ENV
- *(ulong *)CFG_NVRAM_VAR_CRC_ADDR = crc32(0, (char *)environment, env_size);
-#endif
-#if defined(CFG_FLASH_ENV_ADDR)
- MAKEVALID(environment, real_env_size);
-#endif /* CFG_FLASH_ENV_ADDR */
+ /* Update CRC */
+ env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
/* Changes of the Ethernet or IP address should be reflected
* in the board info structure.
_do_setenv (bd, flag, argc, argv);
}
-/* need both ENV and flash */
-#if ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
+/************************************************************************
+ * Look up variable from environment,
+ * return address of storage for that variable,
+ * or NULL if not found
+ */
-void do_saveenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+char *getenv (uchar *name)
{
- int rc;
- extern void flash_sect_protect (int p, ulong addr_first, ulong addr_last);
- extern void flash_sect_erase (ulong addr_first, ulong addr_last);
-#if defined(CFG_FLASH_ENV_BUF)
- uchar *sector_buffer;
-#endif /* CFG_FLASH_ENV_BUF */
+ int i, nxt;
-#if defined(CFG_FLASH_ENV_ADDR)
- uchar *environment = env_init();
-#endif /* CFG_FLASH_ENV_BUF */
+ for (i=0; get_env_char(i) != '\0'; i=nxt+1) {
+ int val;
-#ifdef CONFIG_4xx
- uchar *ed_buf;
+ for (nxt=i; get_env_char(nxt) != '\0'; ++nxt)
+ ;
+ if ((val=envmatch(name, i)) < 0)
+ continue;
+ return (get_env_addr(val));
+ }
- /*
- * On ppc4xx still saved somewhere within a flash sector (no sector
- * reserved for the environment variables). This will be changed in a
- * future release.
- */
- ulong sector_flash_addr;
- ulong sector_flash_size;
- ulong sector_flash_offs;
- int i;
- flash_info_t *info;
-
-# ifndef CFG_FLASH_ENV_ADDR
- env_init();
-# endif
+ return (NULL);
+}
- /*
- * Calculate environment variables sector address and size
- */
- info = addr2info((ulong)flash_addr);
- for (i=0; i<info->sector_count; i++)
- {
- if (info->start[i] >= (ulong)flash_addr)
- break;
- }
- sector_flash_addr = info->start[i-1];
- sector_flash_size = info->start[i] - info->start[i-1];
- sector_flash_offs = (ulong)flash_addr - info->start[i-1];
+int getenv_r (uchar *name, uchar *buf, unsigned len)
+{
+ int i, nxt;
- /*
- * Allocate temp buffer to edit environment
- */
- if ((ed_buf = malloc(sector_flash_size)) == NULL) {
- printf ("## malloc(%lu) failed\n", sector_flash_size);
- return;
+ for (i=0; get_env_char(i) != '\0'; i=nxt+1) {
+ int val, n;
+
+ for (nxt=i; get_env_char(nxt) != '\0'; ++nxt)
+ ;
+ if ((val=envmatch(name, i)) < 0)
+ continue;
+ /* found; copy out */
+ n = 0;
+ while ((len > n++) && (*buf++ = get_env_char(val++)) != '\0')
+ ;
+ if (len == n)
+ *buf = '\0';
+ return (n);
}
+ return (-1);
+}
- /*
- * Copy sector down to ram
- */
- memcpy(ed_buf, (uchar *)sector_flash_addr, sector_flash_size);
- /*
- * Copy new environment variables to ram image of flash sector
- */
- memcpy(ed_buf+sector_flash_offs, (uchar *)environment, env_size);
+/************************************************************************
+ * Match a name / name=value pair
+ *
+ * s1 is either a simple 'name', or a 'name=value' pair.
+ * i2 is the environment index for a 'name=value' pair.
+ * If the names match, return the value of s2, else NULL.
+ */
- flash_sect_protect (0, sector_flash_addr, sector_flash_addr+sector_flash_size-1);
+static int
+envmatch (uchar *s1, int i2)
+{
- printf ("Erasing Flash...");
- flash_sect_erase (sector_flash_addr, sector_flash_addr+sector_flash_size-1);
+ while (*s1 == get_env_char(i2++))
+ if (*s1++ == '=')
+ return(i2);
+ if (*s1 == '\0' && get_env_char(i2-1) == '=')
+ return(i2);
+ return(-1);
+}
- printf ("Saving Environment to Flash...\n");
- switch (rc = flash_write (ed_buf, sector_flash_addr, sector_flash_size)) {
- case 0: break;
- case 1: printf ("Timeout writing to Flash\n");
- break;
- case 2: printf ("Flash not Erased\n");
- break;
- case 4: printf ("Can't write to protected Flash sectors\n");
- break;
- default:
- printf ("%s[%d] FIXME: rc=%d\n",__FILE__,__LINE__,rc);
- }
- free (ed_buf);
+#ifdef CFG_ENV_IS_IN_NVRAM
+
+void do_saveenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ printf ("Saving Environment to NVRAM...\n");
+ memcpy ((char *)CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE);
+}
- flash_sect_protect (1, sector_flash_addr, sector_flash_addr+sector_flash_size-1);
-#else /* ! CONFIG_4xx */
+#elif CFG_ENV_IS_IN_EEPROM
-# ifndef CFG_FLASH_ENV_ADDR
- env_init();
-# endif
+void do_saveenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ printf ("Saving Environment to EEPROM...\n");
+ eeprom_write (CFG_ENV_OFFSET, (uchar *)env_ptr, CFG_ENV_SIZE);
+}
+
+#else /* !CFG_ENV_IS_IN_NVRAM, !CFG_ENV_IS_IN_EEPROM => Must be flash, then */
+
+/* need both ENV and flash */
+#if ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
+
+void do_saveenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
+{
+ int len, rc;
+ ulong end_addr;
+#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE)
+ uchar env_buffer[CFG_ENV_SECT_SIZE];
+#else
+ uchar *env_buffer = (char *)env_ptr;
+#endif /* CFG_ENV_SECT_SIZE */
+
+#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE)
-# if defined(CFG_FLASH_ENV_BUF)
- /* this buffer area was reserved in board_init_f() */
- sector_buffer = (uchar *)((ulong)bd - CFG_FLASH_ENV_BUF);
- /* copy the environment into the sector buffer */
- memcpy(sector_buffer, environment, env_size);
- /* override the old names */
-# define environment sector_buffer
-# define env_size CFG_FLASH_ENV_BUF
-# endif /* CFG_FLASH_ENV_BUF */
+ /* copy old contents to temporary buffer */
+ memcpy(env_buffer, flash_addr, CFG_ENV_SECT_SIZE);
- flash_sect_protect (0, (ulong)flash_addr, (ulong)flash_addr+env_size-1);
+ /* copy current environment to temporary buffer */
+ memcpy(env_buffer, env_ptr, CFG_ENV_SIZE);
+
+ len = CFG_ENV_SECT_SIZE;
+#else
+ len = CFG_ENV_SIZE;
+# endif /* CFG_ENV_SECT_SIZE */
+
+ end_addr = (ulong)flash_addr + len - 1;
+
+ flash_sect_protect (0, (ulong)flash_addr, end_addr);
printf ("Erasing Flash...");
- flash_sect_erase ((ulong)flash_addr, (ulong)flash_addr+env_size-1);
+ flash_sect_erase ((ulong)flash_addr, end_addr);
printf ("Saving Environment to Flash...\n");
- switch (rc = flash_write (environment, (ulong)flash_addr, env_size)) {
+ switch (rc = flash_write(env_buffer, (ulong)flash_addr, len)) {
case 0: break;
case 1: printf ("Timeout writing to Flash\n");
break;
printf ("%s[%d] FIXME: rc=%d\n",__FILE__,__LINE__,rc);
}
- flash_sect_protect (1, (ulong)flash_addr, (ulong)flash_addr+env_size-1);
-
-# if defined(CFG_FLASH_ENV_BUF)
-# undef environment
-# undef env_size
-# endif /* CFG_FLASH_ENV_BUF */
-
-#endif /* CONFIG_4xx */
+ flash_sect_protect (1, (ulong)flash_addr, end_addr);
}
#endif /* CFG_CMD_ENV + CFG_CMD_FLASH */
-/*
- * s1 is either a simple 'name', or a 'name=value' pair.
- * s2 is a 'name=value' pair.
- * If the names match, return the value of s2, else NULL.
- */
+#endif /* CFG_ENV_IS_IN_NVRAM */
-static uchar *
-envmatch (uchar *s1, uchar *s2)
+/************************************************************************
+ * Initialize Environment use
+ *
+ * We are still running from ROM, so data use is limited
+ */
+#ifndef CFG_ENV_IS_IN_EEPROM
+ulong env_init(void)
{
-
- while (*s1 == *s2++)
- if (*s1++ == '=')
- return(s2);
- if (*s1 == '\0' && *(s2-1) == '=')
- return(s2);
- return(NULL);
+ if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
+ return ((ulong)&(env_ptr->data));
+ } else {
+ return ((ulong)&default_environment);
+ }
}
-
+#else /* CFG_ENV_IS_IN_EEPROM */
/*
- * Prevent confusion if running from erased flash memory
+ * Use a (moderately small) buffer on the stack
*/
-#if defined(CFG_FLASH_ENV_ADDR)
-static uchar *env_init(void)
-#else
-static void env_init(void)
-#endif /* CFG_FLASH_ENV_ADDR */
+ulong env_init(void)
{
-#ifdef CONFIG_NVRAM_ENV
- if (crc32(0, (char *)environment, env_size) !=
- *(ulong *)CFG_NVRAM_VAR_CRC_ADDR) {
- int i;
-#if 0 /* still some problems with this printf - don't know why */
- printf ("*** Warning - Environment CRC mismatch, using defaults\n\n");
-#endif
- for (i=0; i<env_size; i++)
- environment[i] = 0x00;
- memcpy (environment,
- default_environment,
- sizeof(default_environment));
- *(ulong *)CFG_NVRAM_VAR_CRC_ADDR =
- crc32(0, (char *)environment, env_size);
- }
-
-#else /* ! CONFIG_NVRAM_ENV */
-
-#if defined(CFG_FLASH_ENV_ADDR)
- /*
- * check if monitor has been relocated yet
- */
- if (environment == rom_addr) {
- /*
- * the monitor is still running from ROM. if the flash copy
- * is valid, use that, otherwise use the default environment
- *
- * NOTE: can't printf here, because getenv() is called from
- * serial_init() (and maybe before that) - hence the serial
- * port is not ready - we can yell later that we are using
- * the default environment... see below.
- */
- if (ISVALID(flash_addr))
- return (flash_addr);
- else
- return (default_environment);
- }
-
- /*
- * the monitor has been relocated - environment will now
- * refer to the "in-memory" copy. If it isn't valid, copy it
- * from the flash, or the default environment, if that isn't
- * valid either.
- */
- if (!ISVALID(environment)) {
- /*
- * "in-memory" copy must be initialised
- */
- if (!ISVALID(flash_addr)) {
- /* flash isn't valid either - use default */
- printf ("\n*** Warning - no Environment,"
- " using defaults\n\n");
- memcpy(environment, default_environment,
- sizeof (default_environment));
- MAKEVALID(environment, env_size);
- }
- else
- /* copy flash environment into RAM */
- memcpy(environment, flash_addr, env_size);
+ ulong crc, len, new;
+ unsigned off;
+ uchar buf[64];
+
+ /* read old CRC */
+ eeprom_read (offsetof(env_t,crc), (uchar *)&crc, sizeof(ulong));
+
+ new = 0;
+ len = ENV_SIZE;
+ off = offsetof(env_t,data);
+ while (len > 0) {
+ int n = (len > sizeof(buf)) ? sizeof(buf) : len;
+
+ eeprom_read (off, buf, n);
+ new = crc32 (new, buf, n);
+ len -= n;
+ off += n;
}
-
- return (environment);
-
-#else /* !CFG_FLASH_ENV_ADDR */
-
- if (environment[0] == 0xFF) {
- printf ("*** Warning - no Environment, using defaults\n\n");
- memcpy (environment,
- default_environment,
- sizeof(default_environment));
+ if (crc == new) {
+ return (offsetof(env_t,data));
+ } else {
+ return (0);
}
-
-#endif /* CFG_FLASH_ENV_ADDR */
-
-#endif /* CONFIG_NVRAM_ENV */
-}
+}
+#endif /* CFG_ENV_IS_IN_EEPROM */
#include <cmd_disk.h>
#include <cmd_console.h>
+#include <cmd_eeprom.h>
+
/*
* HELP command
*/
CMD_TBL_VERS
CMD_TBL_HELP
CMD_TBL_QUES
+
+ CMD_TBL_EEPROM
+
/* the following entry terminates this table */
MK_CMD_TBL_ENTRY( NULL, 0, 0, 0, NULL, NULL, NULL )
};
}
// Called after the relocation - use desierd console functions
-void console_init_r (void)
+void console_init_r (ulong reloc_offset)
{
init_data_t *idata = (init_data_t *)(CFG_INIT_RAM_ADDR + CFG_INIT_DATA_OFFSET);
device_t *inputdev = NULL, *outputdev = NULL ;
return ;
// Set the relocation flag
- idata->relocated = 1 ;
+ idata->relocated = reloc_offset;
}
#include <config.h>
-#ifdef CFG_FLASH_ENV_ADDR
- .set env_not_stored_with_text, 1
-#else
+#if defined(CFG_ENV_IS_IN_FLASH)
+# ifndef CFG_ENV_ADDR
+# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
+# endif
+# ifndef CFG_ENV_OFFSET
+# define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
+# endif
+# ifndef CFG_ENV_SIZE
+# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+# endif
+# if (CFG_ENV_ADDR >= CFG_FLASH_BASE) && \
+ (CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+# define ENV_IS_EMBEDDED
+# endif
+#endif /* CFG_ENV_IS_IN_FLASH */
+
+#ifdef ENV_IS_EMBEDDED
#define XMK_STR(x) #x
#define MK_STR(x) XMK_STR(x)
#endif
.globl environment
environment:
+ .globl env_crc
+env_crc:
+ .long ~0
#ifdef CONFIG_BOOTARGS
.ascii "bootargs="
.ascii CONFIG_BOOTARGS
/* terminate list of environment strings */
.ascii "\0"
- . = environment + CFG_FLASH_ENV_SIZE
+ . = environment + CFG_ENV_SIZE
.L_end:
#if defined(CONFIG_FADS)
.text
env_size:
.long .L_end - environment
.globl env_offset
- .set env_offset, CFG_FLASH_ENV_OFFSET
+ .set env_offset, CFG_ENV_OFFSET
#endif /* CFG_FLASH_ENV_ADDR */
sinclude $(TOPDIR)/$(ARCH)/config.mk # include architecture dependend rules
endif
ifdef CPU
-sinclude $(TOPDIR)/$(CPU)/config.mk # include CPU specific rules
+sinclude $(TOPDIR)/cpu/$(CPU)/config.mk # include CPU specific rules
endif
ifdef BOARD
-sinclude $(TOPDIR)/$(BOARD)/config.mk # include board specific rules
+sinclude $(TOPDIR)/board/$(BOARD)/config.mk # include board specific rules
endif
#########################################################################
RANLIB = $(CROSS_COMPILE)RANLIB
RELFLAGS= $(PLATFORM_RELFLAGS)
-DBGFLAGS= #-g -DDEBUG
+DBGFLAGS= -g #-DDEBUG
OPTFLAGS= -Os -fomit-frame-pointer
-#LDSCRIPT := $(BOARD)/ppcboot.lds.debug
-LDSCRIPT := $(BOARD)/ppcboot.lds
+#LDSCRIPT := board/$(BOARD)/ppcboot.lds.debug
+LDSCRIPT := board/$(BOARD)/ppcboot.lds
CPPFLAGS := $(DBGFLAGS) $(OPTFLAGS) $(RELFLAGS) \
-D__KERNEL__ -D__powerpc__ \
init_data_t *idata =
(init_data_t *)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
- tbclk = (idata->cpu_clk + 3L) / 4L;
+ tbclk = (idata->bus_clk + 3L) / 4L;
return (tbclk);
}
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
u32 cacheon = rd_ic_cst() & IDC_ENABLED;
+#ifdef CONFIG_IP860
+ u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
+#else
u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
+#endif
u32 m;
u32 lines = -1;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
u32 cacheon = rd_dc_cst() & IDC_ENABLED;
+#ifdef CONFIG_IP860
+ u32 k = memctl->memc_br1 & ~0x00007fff; /* probe in flash memoryarea */
+#else
u32 k = memctl->memc_br0 & ~0x00007fff; /* probe in flash memoryarea */
+#endif
u32 m;
u32 lines = -1;
reg |= BR_V; /* then add just the "Bank Valid" bit */
memctl->memc_br0 = reg;
- /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
- * addresses - these have to be modified later when FLASH size
- * has been determined
+ /* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
+ * preliminary addresses - these have to be modified later
+ * when FLASH size has been determined
*/
-#if defined(CONFIG_SPD823TS) || defined(CONFIG_IVMS8) || \
+#if defined(CONFIG_SPD823TS) || \
+ defined(CONFIG_IVMS8) || \
+ defined(CONFIG_HERMES) || \
+ defined(CONFIG_IP860) || \
(defined(CONFIG_MPC860T) && defined(CONFIG_FADS))
/* XXX - FIXME - XXX
* I still don't understand why some systems work only with this
memctl->memc_br1 = CFG_BR1_PRELIM;
#endif
+#if defined(CONFIG_IP860) /* disable CS0 now that Flash is mapped on CS1 */
+ memctl->memc_br0 = 0;
+#endif
+
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
memctl->memc_or2 = CFG_OR2_PRELIM;
memctl->memc_br2 = CFG_BR2_PRELIM;
cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
} RTXBD;
-static RTXBD *rtx;
+static RTXBD *rtx = NULL;
int eth_send(volatile void *packet, int length)
if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
#ifdef ET_DEBUG
- printf("%s[%d] %s: err: %x\n",
- __FILE__,__LINE__,__FUNCTION__,rtx->rxbd[rxIdx].cbd_sc);
+ printf("%s[%d] err: %x\n",
+ __FUNCTION__,__LINE__,rtx->rxbd[rxIdx].cbd_sc);
#endif
} else {
/* Pass the packet up to the protocol layers. */
NetReceive(NetRxPackets[rxIdx], length - 4);
}
-
/* Give the buffer back to the FEC. */
rtx->rxbd[rxIdx].cbd_datlen = 0;
fecp->fec_addr_high = (ea[4] << 8) | (ea[5] ) ;
#undef ea
+ /* Clear multicast address hash table
+ */
+ fecp->fec_hash_table_high = 0;
+ fecp->fec_hash_table_low = 0;
+
+ /* Set maximum receive buffer size.
+ */
+ fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
+
+ /* Set maximum frame length
+ */
+ fecp->fec_r_hash = PKT_MAXBUF_SIZE;
+
+ /*
+ * Setup Buffers and Buffer Desriptors
+ */
rxIdx = 0;
txIdx = 0;
- rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + m8xx_cpm_dpbase_align(8));
-
+ if (!rtx) {
+ rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
+ m8xx_cpm_dpalloc_align(sizeof(RTXBD),8));
+ }
/*
* Setup Receiver Buffer Descriptors (13.14.24.18)
* Settings:
}
rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
- /* Clear multicast address hash table
- */
- fecp->fec_hash_table_high = 0;
- fecp->fec_hash_table_low = 0;
-
- /* Set maximum receive buffer size.
- */
- fecp->fec_r_buff_size = PKT_MAXBLR_SIZE;
-
/* Set receive and transmit descriptor base
*/
fecp->fec_r_des_start = (unsigned int) (&rtx->rxbd[0]);
fecp->fec_x_des_start = (unsigned int) (&rtx->txbd[0]);
- /* Set maximum frame length
- */
- fecp->fec_r_hash = PKT_MAXBUF_SIZE;
-
/* Enable MII mode
*/
#if 0 /* Full duplex mode */
rxIdx = 0;
txIdx = 0;
+#ifdef CFG_DISCOVER_PHY
+ /* wait for the PHY to wake up after reset
+ */
+ mii_discover_phy();
+#endif
+
/* And last, enable the transmit and receive processing
*/
fecp->fec_ecntrl = FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN;
- fecp->fec_r_des_active = 0x01000000;
/* Try to fill Rx Buffer Descriptors */
fecp->fec_r_des_active = 0x01000000; /* Descriptor polling active */
-#ifdef CFG_DISCOVER_PHY
- /* wait for the PHY to wake up after reset
- */
- mii_discover_phy();
-#endif
-
return 1;
}
}
}
}
- if (phyaddr < 0)
+ if (phyaddr < 0) {
printf("No PHY device found.\n");
+ }
}
#endif
#if 0
rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + BD_OFFSET);
#else
- rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + m8xx_cpm_dpbase_align(8));
+ rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
+ m8xx_cpm_dpalloc_align(sizeof(RTXBD), 8));
#endif /* 0 */
#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
* BRO = Reject broadcast packets
* PROMISCOUS = Catch all packets regardless of dest. MAC adress
*/
- immr->im_cpm.cp_scc[SCC_ENET].scc_pmsr = (SCC_PMSR_ENCRC | SCC_PMSR_NIB22
+ immr->im_cpm.cp_scc[SCC_ENET].scc_psmr = (SCC_PMSR_ENCRC | SCC_PMSR_NIB22
/* | SCC_PMSR_BRO | SCC_PMSR_PRO */);
/*
#else
cp->cp_brgc2 = /* Console on SMC2 */
#endif
- ((((cpu_clock / 16) / baudrate)-1) << 1) | CPM_BRG_EN;
+ (((cpu_clock / 16 / baudrate)-1) << 1) | CPM_BRG_EN;
}
void
lis r3, IDC_DISABLE@h /* Disable data cache */
mtspr DC_CST, r3
+#ifndef CONFIG_IP860 /* On IP860, we cannot enable IC yet */
lis r3, IDC_ENABLE@h /* Enable instruction cache */
+#endif
mtspr IC_CST, r3
/* invalidate all tlb's */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Dave Ellis, SIXNET, dge@sixnetio.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+Using the Motorola MPC8XXFADS development board
+===============================================
+
+CONFIGURATIONS
+--------------
+
+There are ready-to-use default configurations available for the
+FADS823, FADS850SAR and FADS860T. The FADS860T configuration also
+works for the 855T processor.
+
+LOADING PPCBOOT INTO FADS FLASH MEMORY
+--------------------------------------
+
+MPC8BUG can load PPCBoot into the FLASH memory using LOADF.
+
+ loadf ppcboot.srec 100000
+
+
+STARTING PPCBOOT FROM MPC8BUG
+-----------------------------
+
+To start PPCBoot from MPC8BUG:
+
+1. Reset the board:
+ reset :h
+
+2. Change BR0 and OR0 back to their values at reset:
+ rms memc br0 00000001
+ rms memc or0 00000d34
+
+3. Modify DER so MPC8BUG gets control only when it should:
+ rms der 2002000f
+
+4. Start as it:
+ go 100
+
+This is NOT exactly the same as starting PPCBoot without
+MPC8BUG. MPC8BUG turns off the watchdog as part of the hard reset.
+After it does the reset it writes SYPCR (to disable the watchdog)
+and sets BR0 and OR0 to map the FLASH at 0x02800000 (and does lots
+of other initialization). That is why it is necessary to set BR0
+and OR0 to map the FLASH everywhere. PPCBoot can't turn on the
+watchdog after that, since MPC8BUG has used the only chance to write
+to SYPCR.
+
+Here is a bizarre sequence of MPC8BUG and PPCBoot commands that lets
+PPCBoot write to SYPCR. It works with MPC8BUG 1.5 and an 855T
+processor (your mileage may vary). It is probably better (and a lot
+easier) just to accept having the watchdog disabled when the debug
+cable is connected.
+
+in MPC8BUG:
+ reset :h
+ rms memc br0 00000001
+ rms memc or0 00000d34
+ rms der 2000f
+ go 100
+
+Now PPCBoot is running with the MPC8BUG value for SYPCR. Use the
+PPCBoot 'reset' command to reset the board.
+ =>reset
+Next, in MPC8BUG:
+ rms der 2000f
+ go
+
+Now PPCBoot is running with the PPCBoot value for SYPCR.
+
typedef struct scc { /* Serial communication channels */
uint scc_gsmrl;
uint scc_gsmrh;
- ushort scc_pmsr;
+ ushort scc_psmr;
char res1[2];
ushort scc_todr;
ushort scc_dsr;
#define CFG_CMD_IRQ 0x00002000 /* irqinfo */
#define CFG_CMD_BOOTD 0x00004000 /* bootd */
#define CFG_CMD_CONSOLE 0x00008000 /* coninfo */
+#define CFG_CMD_EEPROM 0x00010000 /* EEPROM read/write support */
#define CFG_CMD_ALL 0xFFFFFFFF /* ALL commands */
CFG_CMD_IDE | \
CFG_CMD_PCMCIA | \
CFG_CMD_PCI | \
- CFG_CMD_IRQ )
+ CFG_CMD_IRQ | \
+ CFG_CMD_EEPROM )
/* Default configuration
*/
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * EEPROM support
+ */
+#ifndef _CMD_EEPROM_H
+#define _CMD_EEPROM_H
+
+#include <ppcboot.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_EEPROM)
+
+#define CMD_TBL_EEPROM MK_CMD_TBL_ENTRY( \
+ "eeprom", 3, 5, 1, do_eeprom, \
+ "eeprom - EEPROM sub-system", \
+ "read addr off cnt\n" \
+ "eeprom write addr off cnt\n" \
+ " - read/write `cnt' bytes at EEPROM offset `off'\n" \
+),
+
+void do_eeprom (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]);
+
+#else
+
+#define CMD_TBL_EEPROM
+
+#endif /* CFG_CMD_EEPROM */
+
+#endif /* _CMD_EEPROM_H */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
+#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_FR ((ushort)0x0010) /* Framing error */
#define BD_SC_PR ((ushort)0x0008) /* Parity error */
#define BD_SC_OV ((ushort)0x0002) /* Overrun */
-#define BD_SC_CD ((ushort)0x0001) /* ?? */
+#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
/* Parameter RAM offsets.
*/
#endif /* CONFIG_IVMS8 */
+/*** HERMES-PRO ******************************************************/
+
+/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
+
+#ifdef CONFIG_HERMES
+
+#define FEC_ENET /* use FEC for EThernet */
+#undef SCC_ENET
+
+
+#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
+#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
+#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
+#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
+#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
+#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
+#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
+#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
+#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
+#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
+#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
+#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
+#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
+
+#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
+
+#endif /* CONFIG_HERMES */
+
+/*** IP860 **********************************************************/
+
+#if defined(CONFIG_IP860)
+/* Bits in parallel I/O port registers that have to be set/cleared
+ * to configure the pins for SCC1 use.
+ */
+#define PROFF_ENET PROFF_SCC1
+#define CPM_CR_ENET CPM_CR_CH_SCC1
+#define SCC_ENET 0
+#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */
+#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */
+#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
+#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */
+
+#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */
+#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */
+#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */
+
+#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */
+#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */
+
+/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
+ * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
+ */
+#define SICR_ENET_MASK ((uint)0x000000ff)
+#define SICR_ENET_CLKRT ((uint)0x0000002C)
+#endif /* CONFIG_IP860 */
+
/*********************************************************************/
/* SCC Event register as used by Ethernet.
ushort iic_res2; /* reserved */
} iic_t;
+/* HDLC parameter RAM.
+*/
+
+typedef struct hdlc_pram_s {
+ /*
+ * SCC parameter RAM
+ */
+ ushort rbase; /* Rx Buffer descriptor base address */
+ ushort tbase; /* Tx Buffer descriptor base address */
+ uchar rfcr; /* Rx function code */
+ uchar tfcr; /* Tx function code */
+ ushort mrblr; /* Rx buffer length */
+ ulong rstate; /* Rx internal state */
+ ulong rptr; /* Rx internal data pointer */
+ ushort rbptr; /* rb BD Pointer */
+ ushort rcount; /* Rx internal byte count */
+ ulong rtemp; /* Rx temp */
+ ulong tstate; /* Tx internal state */
+ ulong tptr; /* Tx internal data pointer */
+ ushort tbptr; /* Tx BD pointer */
+ ushort tcount; /* Tx byte count */
+ ulong ttemp; /* Tx temp */
+ ulong rcrc; /* temp receive CRC */
+ ulong tcrc; /* temp transmit CRC */
+ /*
+ * HDLC specific parameter RAM
+ */
+ uchar res[4]; /* reserved */
+ ulong c_mask; /* CRC constant */
+ ulong c_pres; /* CRC preset */
+ ushort disfc; /* discarded frame counter */
+ ushort crcec; /* CRC error counter */
+ ushort abtsc; /* abort sequence counter */
+ ushort nmarc; /* nonmatching address rx cnt */
+ ushort retrc; /* frame retransmission cnt */
+ ushort mflr; /* maximum frame length reg */
+ ushort max_cnt; /* maximum length counter */
+ ushort rfthr; /* received frames threshold */
+ ushort rfcnt; /* received frames count */
+ ushort hmask; /* user defined frm addr mask */
+ ushort haddr1; /* user defined frm address 1 */
+ ushort haddr2; /* user defined frm address 2 */
+ ushort haddr3; /* user defined frm address 3 */
+ ushort haddr4; /* user defined frm address 4 */
+ ushort tmp; /* temp */
+ ushort tmp_mb; /* temp */
+} hdlc_pram_t;
+
#define BD_IIC_START ((ushort)0x0400)
/* CPM interrupts. There are nearly 32 interrupts generated by CPM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
-#define CONFIG_NVRAM_ENV 1 /* use NVRAM for environment vars */
-#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
-#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CFG_NVRAM_ENV_SIZE 0x0ffc /* Size of Environment vars */
-#define CFG_NVRAM_VAR_ADDR \
- (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_NVRAM_ENV_SIZE-4) /* Env */
-#define CFG_NVRAM_VAR_CRC_ADDR (CFG_NVRAM_VAR_ADDR+CFG_NVRAM_ENV_SIZE)
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x9000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
+#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
+#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
+#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
+#define CFG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#endif /* CONFIG_WATCHDOG */
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
-/* the other CS:s are determined by looking at parameters in BCSRx */
-
-/* values according to the manual */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
#endif
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
-/* the other CS:s are determined by looking at parameters in BCSRx */
-
-/* values according to the manual */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
#endif
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#undef CONFIG_8xx_CONS_SMC2
#undef CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE 9600
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#if 0
#define MPC8XX_FACT 10 /* Multiply by 10 */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#if 0
-#define CFG_FLASH_ENV_ALIGN 15 /* Bitshift for Environment Sector */
-#endif
-#define CFG_FLASH_ENV_OFFSET 0x00040000
-#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-/* the other CS:s are determined by looking at parameters in BCSRx */
-
-/* values according to the manual */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x00040000
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
#endif
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define FLASH_BASE1_PRELIM 0x0 /* FLASH bank #1 */
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CFG_PRELIM_OR_AM 0xFFF00000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#endif
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x10000 /* Total Size of Environment Sector (64k)*/
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector (64k)*/
/* values according to the manual */
#endif
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
+#define CONFIG_IP860 1 /* ...on a IP860 board */
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE 19200
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "bootm"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_EEPROM)
+
+#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
+
+/*----------------------------------------------------------------------*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x00100000 /* default load address */
+
+#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xF1000000 /* Non-standard value!! */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0x10000000
+#ifdef DEBUG
+#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
+#else
+#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
+#endif
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#undef CFG_ENV_IS_IN_FLASH
+#undef CFG_ENV_IS_IN_NVRAM
+#define CFG_ENV_IS_IN_EEPROM 1
+
+#define CFG_ENV_OFFSET 0 /* Start right at beginning of NVRAM */
+#define CFG_ENV_SIZE 512 /* Use only a part of it - it's slow! */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ * +0x0004
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * +0x0000 => 0x80600800
+ */
+#define CFG_SIUMCR (SIUMCR_EARB | SIUMCR_EARP0 | \
+ SIUMCR_DBGC11 | SIUMCR_MLRC10)
+
+/*-----------------------------------------------------------------------
+ * Clock Setting - the IP860 has no 32kHz clock, so automatic detection fails
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_8xx_GCLK_FREQ 50000000
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ * +0x0200 => 0x00C2
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ * +0x0240 => 0x0082
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* +0x0286 => was: 0x0000D000 */
+#define CFG_PLPRCR \
+ ( PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
+ /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
+ PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
+ )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+/* +0x0282 => 0x02000000 */
+#define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \
+ /*SCCR_RTDIV|*/ /*SCCR_RTSEL|*/ \
+ /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
+ SCCR_EBDF00 | SCCR_DFSYNC00 | \
+ SCCR_DFBRG00 | SCCR_DFNL000 | \
+ SCCR_DFNH000)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+/* +0x0220 => 0x00C3 */
+#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register 19-4
+ *-----------------------------------------------------------------------
+ */
+/* +0x09C4 => TIMEP=1 */
+#define CFG_RCCR 0x0100
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMDS 0
+
+/*-----------------------------------------------------------------------
+ * DER - Debug Event Register
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define CFG_DER 0x2002000F*/
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ */
+
+/*
+ * MAMR settings for SDRAM - 16-14
+ * => 0xC3804114
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA 0xC3
+
+#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+/*
+ * BR1 and OR1 (FLASH)
+ */
+#define FLASH_BASE 0x10000000 /* FLASH bank #0 */
+
+/* used to re-map FLASH
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+/* allow for max 8 MB of Flash */
+#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
+
+#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+/* 16 bit, bank valid */
+#define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
+
+#define CFG_OR1_PRELIM CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM CFG_BR0_PRELIM
+
+/*
+ * BR2/OR2 - SDRAM
+ */
+#define SDRAM_BASE 0x00000000 /* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
+#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
+
+#define CFG_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CFG_BR2 ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR3/OR3 - SRAM (16 bit)
+ */
+#define SRAM_BASE 0x20000000
+#define CFG_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */
+#define CFG_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+
+/*
+ * BR4/OR4 - Board Control & Status (8 bit)
+ */
+#define BCSR_BASE 0xFC000000
+#define CFG_OR4 0xFFFF0120 /* BI (internal) */
+#define CFG_BR4 ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
+
+/*
+ * BR5/OR5 - IP Slot A/B (16 bit)
+ */
+#define IP_SLOT_BASE 0x40000000
+#define CFG_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */
+#define CFG_BR5 ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+
+/*
+ * BR6/OR6 - VME STD (16 bit)
+ */
+#define VME_STD_BASE 0xFE000000
+#define CFG_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */
+#define CFG_BR6 ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+
+/*
+ * BR7/OR7 - SHORT I/O + RTC + IACK (16 bit)
+ */
+#define VME_SHORT_BASE 0xFF000000
+#define CFG_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */
+#define CFG_BR7 ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
+
+/*-----------------------------------------------------------------------
+ * Board Control and Status Region:
+ *-----------------------------------------------------------------------
+ */
+#ifndef __ASSEMBLY__
+typedef struct ip860_bcsr_s {
+ uchar shmem_addr; /* +00 shared memory address register */
+ uchar reserved0;
+ uchar mbox_addr; /* +02 mailbox address register */
+ uchar reserved1;
+ uchar vme_int_mask; /* +04 VME Bus interrupt mask register */
+ uchar reserved2;
+ uchar vme_int_pend; /* +06 VME interrupt pending register */
+ uchar reserved3;
+ uchar bd_int_mask; /* +08 board interrupt mask register */
+ uchar reserved4;
+ uchar bd_int_pend; /* +0A board interrupt pending register */
+ uchar reserved5;
+ uchar bd_ctrl; /* +0C board control register */
+ uchar reserved6;
+ uchar bd_status; /* +0E board status register */
+ uchar reserved7;
+ uchar vme_irq; /* +10 VME interrupt request register */
+ uchar reserved8;
+ uchar vme_ivec; /* +12 VME interrupt vector register */
+ uchar reserved9;
+ uchar cli_mbox; /* +14 clear mailbox irq */
+ uchar reservedA;
+ uchar rtc; /* +16 RTC control register */
+ uchar reservedB;
+ uchar mbox_data; /* +18 mailbox read/write register */
+ uchar reservedC;
+ uchar wd_trigger; /* +1A Watchdog trigger register */
+ uchar reservedD;
+ uchar rmw_req; /* +1C RMW request register */
+} ip860_bcsr_t;
+#endif /* __ASSEMBLY__ */
+
+/*-----------------------------------------------------------------------
+ * Board Control Register: bd_ctrl (Offset 0x0C)
+ *-----------------------------------------------------------------------
+ */
+#define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */
+#define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */
+#define BD_CTRL_FLWE 0x20 /* Flash Write Enable */
+#define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
-
-#define CFG_FLASH_ENV_ADDR (CFG_FLASH_BASE+CFG_FLASH_ENV_OFFSET)
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#endif
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
-
/*-----------------------------------------------------------------------
* NVRAM Configuration
*
* board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
* access the NVRAM at the offset 0x1000.
*/
-#define CONFIG_NVRAM_ENV 1 /* turn on NVRAM env feature */
-#define CFG_NVRAM_VAR_ADDR (CFG_NVRAM_BASE + 0x1000)
-#define CFG_NVRAM_ENV_SIZE 0x0ffc
-#define CFG_NVRAM_VAR_CRC_ADDR (CFG_NVRAM_VAR_ADDR + CFG_NVRAM_ENV_SIZE)
+#define CFG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */
+#define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000)
+#define CFG_ENV_SIZE 0x1000
/*-----------------------------------------------------------------------
* Cache Configuration
#endif
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#endif
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x0800 /* Total Size of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#endif
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_ALIGN 15 /* Bitshift for Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
-/* the other CS:s are determined by looking at parameters in BCSRx */
-
-/* values according to the manual */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
#endif
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
#endif
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
#endif
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
-#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/*-----------------------------------------------------------------------
* Cache Configuration
#endif
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
#error 2nd dual serial capability defined without serial/parallel capability
#endif
-#include <cogent/mb.h>
+#include <board/cogent/mb.h>
#endif /* _CONFIG_COGENT_COMMON_H */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */
#ifdef CONFIG_CMA302
-#define CFG_FLASH_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CFG_FLASH_ENV_BUF (512*1024) /* see README - env sect real size */
+#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
#else
-#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-#define CFG_FLASH_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */
#ifdef CONFIG_CMA302
-#define CFG_FLASH_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CFG_FLASH_ENV_BUF (512*1024) /* see README - env sect real size */
+#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
#else
-#define CFG_FLASH_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
#endif /* CONFIG_WATCHDOG */
/*-----------------------------------------------------------------------
- * SUMCR - SIU Module Configuration 11-6
+ * SIUMCR - SIU Module Configuration 11-6
*-----------------------------------------------------------------------
* PCMCIA config., multi-function pin tri-state
*/
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
+#define CONFIG_HERMES 1 /* ...on a HERMES-PRO board */
+
+#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
+#undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_NONE
+#define CONFIG_BAUDRATE 9600
+#if 0
+#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
+#else
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND \
+ "bootp; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+ "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "bootm"
+
+#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
+#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
+
+#undef CONFIG_WATCHDOG /* watchdog disabled */
+
+#define CONFIG_COMMANDS CONFIG_CMD_DFL
+
+#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
+
+/*----------------------------------------------------------------------*/
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*----------------------------------------------------------------------*/
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x00100000 /* default load address */
+
+#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR 0xFF000000 /* Non-Standard value! */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR CFG_IMMR
+#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
+#define CFG_INIT_DATA_SIZE 64 /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_INIT_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_FLASH_BASE 0xFE000000
+#ifdef DEBUG
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
+#else
+#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
+#endif
+#define CFG_MONITOR_BASE CFG_FLASH_BASE
+#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
+#define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */
+
+#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
+
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_OFFSET 0x4000 /* Offset of Environment Sector */
+#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control 11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ * +0x0004
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+ SYPCR_SWE | SYPCR_SWP)
+#else
+#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration 11-6
+ *-----------------------------------------------------------------------
+ * +0x0000 => 0x000000C0
+ */
+#define CFG_SIUMCR 0 //XXX-wd-XXX (SIUMCR_BSC | SIUMCR_GB5E)
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control 11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ * +0x0200 => 0x00C2
+ */
+#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control 11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ * +0x0240 => 0x0082
+ */
+#define CFG_PISCR (PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit, set PLL multiplication factor !
+ */
+/* +0x0286 => 0x00B0D0C0 */
+#define CFG_PLPRCR \
+ ( (11 << PLPRCR_MF_SHIFT) | \
+ PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
+ /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
+ PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
+ )
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register 15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK SCCR_EBDF11
+/* +0x0282 => 0x03800000 */
+#define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \
+ SCCR_RTDIV | SCCR_RTSEL | \
+ /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
+ SCCR_EBDF00 | SCCR_DFSYNC00 | \
+ SCCR_DFBRG00 | SCCR_DFNL000 | \
+ SCCR_DFNH000)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register 11-27
+ *-----------------------------------------------------------------------
+ */
+/* +0x0220 => 0x00C3 */
+#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration Register 19-4
+ *-----------------------------------------------------------------------
+ */
+/* +0x09C4 => TIMEP=1 */
+#define CFG_RCCR 0x0100
+
+/*-----------------------------------------------------------------------
+ * RMDS - RISC Microcode Development Support Control Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMDS 0
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+/*#define CFG_DER 0x2002000F*/
+#define CFG_DER 0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0 and OR0 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
+
+/* used to re-map FLASH
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+/* allow for max 4 MB of Flash */
+#define CFG_REMAP_OR_AM 0xFFC00000 /* OR addr mask */
+#define CFG_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
+
+/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 1, SCY = 5, EHTR = 0 */
+#define CFG_OR_TIMING_FLASH ( OR_CSNT_SAM | /*OR_ACS_DIV4 |*/ OR_BI | \
+ OR_SCY_5_CLK | OR_TRLX)
+
+#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+/* 8 bit, bank valid */
+#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR1/OR1 - SDRAM
+ *
+ * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
+ */
+#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank */
+#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
+#define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */
+
+#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
+
+#define CFG_OR1_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
+#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+/*
+ * BR2/OR2 - HPRO2: PEB2256 @ 0xE0000000, 8 Bit wide
+ */
+#define HPRO2_BASE 0xE0000000
+#define HPRO2_OR_AM 0xFFFF8000
+#define HPRO2_TIMING 0x00000934
+
+#define CFG_OR2 (HPRO2_OR_AM | HPRO2_TIMING)
+#define CFG_BR2 ((HPRO2_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+
+/*
+ * BR3/OR3: not used
+ * BR4/OR4: not used
+ * BR5/OR5: not used
+ * BR6/OR6: not used
+ * BR7/OR7: not used
+ */
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* periodic timer for refresh */
+#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
+ MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
+ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#endif /* __CONFIG_H */
#define CONFIG_BAUDRATE 9600
#endif
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~(CFG_CMD_NET|CFG_CMD_KGDB|CFG_CMD_IDE|CFG_CMD_PCI))
+#define CONFIG_COMMANDS (CFG_CMD_ALL & \
+ ~(CFG_CMD_NET|CFG_CMD_KGDB|CFG_CMD_IDE|CFG_CMD_PCI|CFG_CMD_EEPROM))
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
#define CFG_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
-#define CFG_FLASH_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CFG_FLASH_ENV_BUF 0x40000 /* see README - env sect real size */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
+#define CFG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */
+/* XXX The following #define is probably wrong, but you MUST either
+ * XXX #define CFG_ENV_ADDR or CFG_ENV_OFFSET
+ */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
/*-----------------------------------------------------------------------
* Cache Configuration
/* Prototypes */
unsigned long flash_init (void);
-void flash_print_info (flash_info_t *);
-void flash_erase (flash_info_t *, int, int);
+void flash_print_info (flash_info_t *);
+void flash_erase (flash_info_t *, int, int);
+void flash_sect_erase (ulong addr_first, ulong addr_last);
+void flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
/*-----------------------------------------------------------------------
* Device IDs for AMD and Fujitsu FLASH
#define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */
#define MT_ID_28F400_B 0x44714471 /* 28F400B3 ID ( 4 M, bottom boot sect) */
+#define INTL_ID_28F016S 0x66a066a0 /* 28F016S[VS] ID (16M = 512k x 16) */
+
#define AMD_ID_F040B 0xA4 /* 29F040B ID ( 4 M, bottom boot sect) */
#define AMD_ID_F080B 0xD5 /* 29F0B0 ID ( 1 M) */
/*-----------------------------------------------------------------------
* Internal FLASH identification codes
+ *
+ * Be careful when adding new type! Odd numbers are "bottom boot sector" types!
*/
#define FLASH_AM040T 0x0000 /* AMD AM29F040 */
#define FLASH_28F400_B 0x0023 /* MT 28F400B3 ID ( 4M = 256K x 16 ) */
#define FLASH_28F008S5 0x0050 /* Intel 28F008S5 ( 1M = 64K x 16 ) */
-#define FLASH_28F800_B 0x0051 /* Intel E28F800B ( 1M = ? ) */
-#define FLASH_AM29F800B 0x0052 /* AMD Am29F800BB ( 1M = ? ) */
+#define FLASH_28F016SV 0x0051 /* Intel 28F016SV (16M = 512k x 16 ) */
+#define FLASH_28F800_B 0x0053 /* Intel E28F800B ( 1M = ? ) */
+#define FLASH_AM29F800B 0x0054 /* AMD Am29F800BB ( 1M = ? ) */
#define FLASH_UNKNOWN 0xFFFF /* unknown flash type */
/* with AMD, Fujitsu and SST */
/* (JEDEC standard commands ?) */
-#define FLASH_BTYPE 0x01 /* mask for bottom boot sector type */
+#define FLASH_BTYPE 0x0001 /* mask for bottom boot sector type */
/*-----------------------------------------------------------------------
* Timeout constants:
/*-----------------------------------------------------------------------
* SIUMCR - SIU Module Configuration Register 11-6
*/
-#define SIUMCR_EARB 0x80000000 /* External Arbitation */
-#define SIUMCR_EARP111 0x70000000 /* Extern Arbi. Request prior. */
+#define SIUMCR_EARB 0x80000000 /* External Arbitration */
+#define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */
+#define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */
+#define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */
+#define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */
+#define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */
+#define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */
+#define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */
+#define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */
#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */
#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */
#define SIUMCR_DBGC01 0x00200000 /* - " - */
#define BR_BA_MSK 0xffff8000 /* Base Address Mask */
#define BR_AT_MSK 0x00007000 /* Address Type Mask */
#define BR_PS_MSK 0x00000c00 /* Port Size Mask */
+#define BR_PS_32 0x00000000 /* 32 bit port size */
+#define BR_PS_16 0x00000800 /* 16 bit port size */
+#define BR_PS_8 0x00000400 /* 8 bit port size */
#define BR_PARE 0x00000200 /* Parity Enable */
#define BR_WP 0x00000100 /* Write Protect */
#define BR_MS_MSK 0x000000c0 /* Machine Select Mask */
#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
#define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */
#define BR_V 0x00000001 /* Bank Valid */
-#define BR_PS_8 0x00000400 /* 8 bit port size */
-#define BR_PS_16 0x00000800 /* 16 bit port size */
-#define BR_PS_32 0x00000000 /* 32 bit port size */
/*-----------------------------------------------------------------------
* OR - Memory Controler: Option Register 16-11
#undef _LINUX_CONFIG_H
#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
+typedef unsigned char uchar;
+typedef volatile unsigned long vu_long;
+typedef volatile unsigned short vu_short;
+
#include "config.h"
#include <linux/bitops.h>
#include <linux/types.h>
#include <ppc4xx.h>
#endif
-typedef unsigned char uchar;
-typedef volatile unsigned long vu_long;
-typedef volatile unsigned short vu_short;
-
#include <flash.h>
#include <image.h>
unsigned long bi_bootflags; /* boot / reboot flag (for LynxOS) */
unsigned long bi_ip_addr; /* IP Address */
unsigned char bi_enetaddr[6]; /* Ethernet adress */
- unsigned char bi_reserved[2]; /* -- just for alignment -- */
+ unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
#if defined(CONFIG_8260)
unsigned long scc_clk;
unsigned long brg_clk;
unsigned long cpu_clk;
- /* contents of reset status register at boot */
- unsigned long reset_status;
+ unsigned long reset_status; /* reset status register at boot */
#endif
- unsigned long relocated; /* Set when relocated to RAM */
+ unsigned long env_addr; /* Address of Environment struct */
+ unsigned long relocated; /* Relocat. offset when running in RAM */
mon_fnc_t bi_mon_fnc; /* Monitor functions */
#ifdef CONFIG_8xx
unsigned int dp_alloc_base;
extern ulong load_addr; /* Default Load Address */
/* common/cmd_nvedit.c */
+ulong env_init (void);
+void env_relocate (ulong);
char *getenv (uchar *);
+int getenv_r (uchar *name, uchar *buf, unsigned len);
void inline setenv (char *, char *);
/* board/flash.c */
void pciinfo (int);
#endif
-#ifdef CONFIG_SPD823TS
-/* $(BOARD)/spd8xx.c */
+#if defined(CONFIG_SPD823TS) || defined(CONFIG_IVMS8) || defined(CONFIG_IP860)
+/* $(BOARD)/$(BOARD).c */
void reset_phy (void);
#endif
+#if defined(CONFIG_IP860)
+/* $(BOARD)/eeprom.c */
+void eeprom_init (void);
+void eeprom_read (unsigned offset, uchar *buffer, unsigned cnt);
+void eeprom_write (unsigned offset, uchar *buffer, unsigned cnt);
+#endif
+
#ifdef CONFIG_MBX
/* $(BOARD)/mbx8xx.c */
void mbx_init (void);
void board_ether_init (void);
#endif
+#ifdef CONFIG_HERMES
+/* $(BOARD)/hermes.c */
+void hermes_set_led (int);
+void hermes_show_led_err (int);
+void hermes_flash_led (void);
+void hermes_start_lxt980 (int speed);
+#endif
+
/* $(CPU)/serial.c */
void serial_init (ulong, int);
void serial_setbrg (ulong, int);
bd_t *bd_ptr ;
void console_init_f(void); /* Before relocation; uses the serial stuff */
-void console_init_r(void); /* After relocation; uses the console stuff */
+void console_init_r(ulong); /* After relocation; uses the console stuff */
int console_assign (int file, char *devname); /* Assign the console */
/*
#ifndef __VERSION_H__
#define __VERSION_H__
-#define PPCBOOT_VERSION "ppcboot 0.6.4"
+#define PPCBOOT_VERSION "ppcboot 0.7.0"
#endif /* __VERSION_H__ */
* For conditions of distribution and use, see copyright notice in zlib.h
*/
-/* @(#) $Id: crc32.c,v 1.1 2000/07/18 08:54:27 wd Exp $ */
-
#include "zlib.h"
#define local static
projects / users / rw / ppcboot.git / commitdiff