dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-mallow.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb
 
+imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtbo
+imx8mp-evk-lvds0-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds0-imx-lvds-hdmi.dtbo
+imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtbo
+imx8mp-evk-lvds1-imx-lvds-hdmi-dtbs += imx8mp-evk.dtb imx8mp-evk-lvds1-imx-lvds-hdmi.dtbo
 imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo
 imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx8mp-evk-pcie-ep.dtbo
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-dlvds-hdmi-channel0.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds0-imx-lvds-hdmi.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-dlvds-hdmi-channel0.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-lvds1-imx-lvds-hdmi.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-mx8-dlvds-lcd1.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie-ep.dtb
 
 
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+/dts-v1/;
+/plugin/;
+
+&{/} {
+       lvds-hdmi-connector {
+               compatible = "hdmi-connector";
+               label = "J2";
+               type = "a";
+
+               port {
+                       lvds2hdmi_connector_in: endpoint {
+                               remote-endpoint = <&it6263_out>;
+                       };
+               };
+       };
+};
+
+&lcdif2 {
+       status = "okay";
+};
+
+&lvds_bridge {
+       status = "okay";
+};
 
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+       ports {
+               port@0 {
+                       reg = <0>;
+                       dual-lvds-odd-pixels;
+
+                       it6263_lvds_link1: endpoint {
+                               remote-endpoint = <&ldb_lvds_ch0>;
+                       };
+               };
+
+               port@1 {
+                       reg = <1>;
+                       dual-lvds-even-pixels;
+
+                       it6263_lvds_link2: endpoint {
+                               remote-endpoint = <&ldb_lvds_ch1>;
+                       };
+               };
+       };
+};
+
+&lvds_bridge {
+       ports {
+               port@1 {
+                       ldb_lvds_ch0: endpoint {
+                               remote-endpoint = <&it6263_lvds_link1>;
+                       };
+               };
+
+               port@2 {
+                       ldb_lvds_ch1: endpoint {
+                               remote-endpoint = <&it6263_lvds_link2>;
+                       };
+               };
+       };
+};
 
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi"
+
+&i2c2 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       it6263: hdmi@4c {
+               compatible = "ite,it6263";
+               reg = <0x4c>;
+               data-mapping = "jeida-24";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_lvds_en>;
+               reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+               ivdd-supply = <®_buck5>;
+               ovdd-supply = <®_vext_3v3>;
+               txavcc18-supply = <®_buck5>;
+               txavcc33-supply = <®_vext_3v3>;
+               pvcc1-supply = <®_buck5>;
+               pvcc2-supply = <®_buck5>;
+               avcc-supply = <®_vext_3v3>;
+               anvdd-supply = <®_buck5>;
+               apvdd-supply = <®_buck5>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@2 {
+                               reg = <2>;
+
+                               it6263_out: endpoint {
+                                       remote-endpoint = <&lvds2hdmi_connector_in>;
+                               };
+                       };
+               };
+       };
+};
 
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds0-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+       ports {
+               port@0 {
+                       reg = <0>;
+
+                       it6263_lvds_link1: endpoint {
+                               remote-endpoint = <&ldb_lvds_ch0>;
+                       };
+               };
+       };
+};
+
+&lvds_bridge {
+       ports {
+               port@1 {
+                       ldb_lvds_ch0: endpoint {
+                               remote-endpoint = <&it6263_lvds_link1>;
+                       };
+               };
+       };
+};
 
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+       ports {
+               port@0 {
+                       reg = <0>;
+                       dual-lvds-even-pixels;
+
+                       it6263_lvds_link1: endpoint {
+                               remote-endpoint = <&ldb_lvds_ch1>;
+                       };
+               };
+
+               port@1 {
+                       reg = <1>;
+                       dual-lvds-odd-pixels;
+
+                       it6263_lvds_link2: endpoint {
+                               remote-endpoint = <&ldb_lvds_ch0>;
+                       };
+               };
+       };
+};
+
+&lvds_bridge {
+       ports {
+               port@1 {
+                       ldb_lvds_ch0: endpoint {
+                               remote-endpoint = <&it6263_lvds_link2>;
+                       };
+               };
+
+               port@2 {
+                       ldb_lvds_ch1: endpoint {
+                               remote-endpoint = <&it6263_lvds_link1>;
+                       };
+               };
+       };
+};
 
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "imx8mp-evk-imx-lvds-hdmi-common.dtsi"
+
+&i2c3 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       it6263: hdmi@4c {
+               compatible = "ite,it6263";
+               reg = <0x4c>;
+               data-mapping = "jeida-24";
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_lvds_en>;
+               reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+               ivdd-supply = <®_buck5>;
+               ovdd-supply = <®_vext_3v3>;
+               txavcc18-supply = <®_buck5>;
+               txavcc33-supply = <®_vext_3v3>;
+               pvcc1-supply = <®_buck5>;
+               pvcc2-supply = <®_buck5>;
+               avcc-supply = <®_vext_3v3>;
+               anvdd-supply = <®_buck5>;
+               apvdd-supply = <®_buck5>;
+
+               ports {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       port@2 {
+                               reg = <2>;
+
+                               it6263_out: endpoint {
+                                       remote-endpoint = <&lvds2hdmi_connector_in>;
+                               };
+                       };
+               };
+       };
+};
 
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2024 NXP
+ */
+
+#include "imx8mp-evk-lvds1-imx-lvds-hdmi-common.dtsi"
+
+&it6263 {
+       ports {
+               port@0 {
+                       reg = <0>;
+
+                       it6263_lvds_link1: endpoint {
+                               remote-endpoint = <&ldb_lvds_ch1>;
+                       };
+               };
+       };
+};
+
+&lvds_bridge {
+       ports {
+               port@2 {
+                       ldb_lvds_ch1: endpoint {
+                               remote-endpoint = <&it6263_lvds_link1>;
+                       };
+               };
+       };
+};
 
                >;
        };
 
+       pinctrl_lvds_en: lvdsengrp {
+               fsl,pins = <
+                       MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10     0x1c0
+               >;
+       };
+
        pinctrl_pcie0: pcie0grp {
                fsl,pins = <
                        MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B    0x60 /* open drain, pull up */