int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev)
 {
-       struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
-       struct smu_context *smu = adev->powerplay.pp_handle;
+       if (is_support_sw_smu(adev)) {
+               struct smu_context *smu = adev->powerplay.pp_handle;
+
+               return (smu->od_enabled || smu->is_apu);
+       } else {
+               struct pp_hwmgr *hwmgr;
 
-       if ((is_support_sw_smu(adev) && smu->od_enabled) ||
-           (is_support_sw_smu(adev) && smu->is_apu) ||
-               (!is_support_sw_smu(adev) && hwmgr->od_enabled))
-               return true;
+               /* SI asic does not carry od_enabled */
+               if (adev->family == AMDGPU_FAMILY_SI)
+                       return false;
 
-       return false;
+               hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle;
+
+               return hwmgr->od_enabled;
+       }
 }
 
 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev,