#define IEN(off)               (0x1800 + (off) * 8)
 #define PUPD(off)              (0x1C00 + (off) * 8)
 #define ISEL(off)              (0x2C00 + (off) * 8)
+#define NOD(off)               (0x3000 + (off) * 8)
 #define SD_CH(off, ch)         ((off) + (ch) * 4)
 #define ETH_POC(off, ch)       ((off) + (ch) * 4)
 #define QSPI                   (0x3008)
 #define IOLH_MASK              0x03
 #define SR_MASK                        0x01
 #define PUPD_MASK              0x03
+#define NOD_MASK               0x01
 
 #define PM_INPUT               0x1
 #define PM_OUTPUT              0x2
                break;
        }
 
+       case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+       case PIN_CONFIG_DRIVE_PUSH_PULL:
+               if (!(cfg & PIN_CFG_NOD))
+                       return -EINVAL;
+
+               arg = rzg2l_read_pin_config(pctrl, NOD(off), bit, NOD_MASK);
+               if (!arg && param != PIN_CONFIG_DRIVE_PUSH_PULL)
+                       return -EINVAL;
+               if (arg && param != PIN_CONFIG_DRIVE_OPEN_DRAIN)
+                       return -EINVAL;
+               break;
+
        case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
                if (!(cfg & PIN_CFG_IOLH_RZV2H))
                        return -EINVAL;
                        rzg2l_rmw_pin_config(pctrl, IOLH(off), bit, IOLH_MASK, index);
                        break;
 
+               case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+               case PIN_CONFIG_DRIVE_PUSH_PULL:
+                       if (!(cfg & PIN_CFG_NOD))
+                               return -EINVAL;
+
+                       rzg2l_rmw_pin_config(pctrl, NOD(off), bit, NOD_MASK,
+                                            param == PIN_CONFIG_DRIVE_OPEN_DRAIN ? 1 : 0);
+                       break;
+
                case RENESAS_RZV2H_PIN_CONFIG_OUTPUT_IMPEDANCE:
                        if (!(cfg & PIN_CFG_IOLH_RZV2H))
                                return -EINVAL;