case SOC15_IH_CLIENTID_SE3SH:
        case SOC15_IH_CLIENTID_UTCL2:
                block = AMDGPU_RAS_BLOCK__GFX;
-               reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
+               if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
+                       reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
+               else
+                       reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
                break;
        case SOC15_IH_CLIENTID_VMC:
        case SOC15_IH_CLIENTID_VMC1:
        case SOC15_IH_CLIENTID_SDMA3:
        case SOC15_IH_CLIENTID_SDMA4:
                block = AMDGPU_RAS_BLOCK__SDMA;
-               reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
+               if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3))
+                       reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET;
+               else
+                       reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET;
                break;
        default:
                dev_warn(dev->adev->dev,