return 0;
 }
 
+static int gfx_v11_0_ras_late_init(void *handle)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct ras_common_if *gfx_common_if;
+       int ret;
+
+       gfx_common_if = kzalloc(sizeof(struct ras_common_if), GFP_KERNEL);
+       if (!gfx_common_if)
+               return -ENOMEM;
+
+       gfx_common_if->block = AMDGPU_RAS_BLOCK__GFX;
+
+       ret = amdgpu_ras_feature_enable(adev, gfx_common_if, true);
+       if (ret)
+               dev_err(adev->dev, "Failed to enable gfx11 ras feature\n");
+
+       kfree(gfx_common_if);
+       return ret;
+}
+
 static int gfx_v11_0_late_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        if (r)
                return r;
 
+       if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(11, 0, 3)) {
+               r = gfx_v11_0_ras_late_init(handle);
+               if (r)
+                       return r;
+       }
+
        return 0;
 }