drm/amdgpu: pre-map device buffer as cached for A+A config

For A+A configuration, device memory is supposed to be mapped as
cachable from CPU side. For kernel pre-map gpu device memory using
ioremap_cache

Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Reviewed-by: Christian Koenig <Christian.Koenig@amd.com>
Tested-by: Amber Lin <Amber.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index f2b0094f1eaf0820416644698a8b8a27b502940b..4add9eaa7fa45cd00ee313bfdf1303265b8bf4e9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1811,8 +1811,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
        /* Change the size here instead of the init above so only lpfn is affected */
        amdgpu_ttm_set_buffer_funcs_status(adev, false);
 #ifdef CONFIG_64BIT
-       adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
-                                               adev->gmc.visible_vram_size);
+       if (adev->gmc.xgmi.connected_to_cpu)
+               adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
+                               adev->gmc.visible_vram_size);
+
+       else
+               adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
+                               adev->gmc.visible_vram_size);
 #endif
 
        /*