ARM: Factor out common code from cpu_proc_fin()

All implementations of cpu_proc_fin() start by disabling interrupts
and then flush caches.  Rather than have every processors proc_fin()
implementation do this, move it out into generic code - and move the
cache flush past setup_mm_for_reboot() (so it can benefit from having
caches still enabled.)

This allows cpu_proc_fin() to become independent of the L1/L2 cache
types, and eventually move the L2 cache flushing into the L2 support
code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 598ca61e7bca8496a853128a433dc7d1dfba0edf..3b4872c2da8e51055acad62564c4e6a220e8000b 100644 (file)
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -74,7 +74,11 @@ void machine_kexec(struct kimage *image)
                           (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
        printk(KERN_INFO "Bye!\n");
 
-       cpu_proc_fin();
+       local_irq_disable();
+       local_fiq_disable();
        setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
+       flush_cache_all();
+       cpu_proc_fin();
+       flush_cache_all();
        cpu_reset(reboot_code_buffer_phys);
 }

diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index a4a9cc88bec73a525a9edd4bdc7db94cea370ce9..aaf51159203af6b721bc8710c3ab5a6bab61cd77 100644 (file)
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -29,6 +29,7 @@
 #include <linux/utsname.h>
 #include <linux/uaccess.h>
 
+#include <asm/cacheflush.h>
 #include <asm/leds.h>
 #include <asm/processor.h>
 #include <asm/system.h>
@@ -84,10 +85,9 @@ __setup("hlt", hlt_setup);
 
 void arm_machine_restart(char mode, const char *cmd)
 {
-       /*
-        * Clean and disable cache, and turn off interrupts
-        */
-       cpu_proc_fin();
+       /* Disable interrupts first */
+       local_irq_disable();
+       local_fiq_disable();
 
        /*
         * Tell the mm system that we are going to reboot -
@@ -96,6 +96,15 @@ void arm_machine_restart(char mode, const char *cmd)
         */
        setup_mm_for_reboot(mode);
 
+       /* Clean and invalidate caches */
+       flush_cache_all();
+
+       /* Turn off caching */
+       cpu_proc_fin();
+
+       /* Push out any further dirty data, and ensure cache is empty */
+       flush_cache_all();
+
        /*
         * Now call the architecture specific reboot code.
         */

diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 72507c630ceb563e9242145722b542b52731a7b3..203a4e944d9e43c53051725c084f542cceb8b7a3 100644 (file)
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020_proc_init)
  * cpu_arm1020_proc_fin()
  */
 ENTRY(cpu_arm1020_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm1020_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm1020_reset(loc)

diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index d27829805609f5793e23bb2fd0c67ac85993e955..1a511e765909957d81b463c17f0000b8893d3770 100644 (file)
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -79,15 +79,11 @@ ENTRY(cpu_arm1020e_proc_init)
  * cpu_arm1020e_proc_fin()
  */
 ENTRY(cpu_arm1020e_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm1020e_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm1020e_reset(loc)

diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index ce13e4a827de8ed9e787b11bf3a784b0bf803dab..1ffa4eb9c34f7d7d2f1b5ad5e3825daf67d14156 100644 (file)
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -68,15 +68,11 @@ ENTRY(cpu_arm1022_proc_init)
  * cpu_arm1022_proc_fin()
  */
 ENTRY(cpu_arm1022_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm1022_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm1022_reset(loc)

diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 636672a29c6d1e58ad905850cba7374ba09d8f45..5697c34b95b0cdb38c31aad752c172b6990b5567 100644 (file)
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -68,15 +68,11 @@ ENTRY(cpu_arm1026_proc_init)
  * cpu_arm1026_proc_fin()
  */
 ENTRY(cpu_arm1026_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm1026_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm1026_reset(loc)

diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 795dc615f43bb6f4b6513f4ac6a17a287911876e..64e0b327c7c5f504ec00757dcfd832d1fe56ac9e 100644 (file)
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -184,8 +184,6 @@ ENTRY(cpu_arm7_proc_init)
 
 ENTRY(cpu_arm6_proc_fin)
 ENTRY(cpu_arm7_proc_fin)
-               mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-               msr     cpsr_c, r0
                mov     r0, #0x31                       @ ....S..DP...M
                mcr     p15, 0, r0, c1, c0, 0           @ disable caches
                mov     pc, lr

diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 0b62de24466646d8b7e8aa65b84e8ac5191335f5..9d96824134fc4db4b0cd24f9df65c405717b4341 100644 (file)
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -54,15 +54,11 @@ ENTRY(cpu_arm720_proc_init)
                mov     pc, lr
 
 ENTRY(cpu_arm720_proc_fin)
-               stmfd   sp!, {lr}
-               mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-               msr     cpsr_c, ip
                mrc     p15, 0, r0, c1, c0, 0
                bic     r0, r0, #0x1000                 @ ...i............
                bic     r0, r0, #0x000e                 @ ............wca.
                mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-               mcr     p15, 0, r1, c7, c7, 0           @ invalidate cache
-               ldmfd   sp!, {pc}
+               mov     pc, lr
 
 /*
  * Function: arm720_proc_do_idle(void)

diff --git a/arch/arm/mm/proc-arm740.S b/arch/arm/mm/proc-arm740.S
index 01860cdeb2ec3df451947f325c7d132449820717..6c1a9ab059aedb2f48e0d2bff8b823b3bb306dab 100644 (file)
--- a/arch/arm/mm/proc-arm740.S
+++ b/arch/arm/mm/proc-arm740.S
@@ -36,15 +36,11 @@ ENTRY(cpu_arm740_switch_mm)
  * cpu_arm740_proc_fin()
  */
 ENTRY(cpu_arm740_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
        mrc     p15, 0, r0, c1, c0, 0
        bic     r0, r0, #0x3f000000             @ bank/f/lock/s
        bic     r0, r0, #0x0000000c             @ w-buffer/cache
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       mcr     p15, 0, r0, c7, c0, 0           @ invalidate cache
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm740_reset(loc)

diff --git a/arch/arm/mm/proc-arm7tdmi.S b/arch/arm/mm/proc-arm7tdmi.S
index 1201b98638298087063d3ec02eefd3a7e58d9aa6..6a850dbba22e5ff7be9aae70476489feeaaeef18 100644 (file)
--- a/arch/arm/mm/proc-arm7tdmi.S
+++ b/arch/arm/mm/proc-arm7tdmi.S
@@ -36,8 +36,6 @@ ENTRY(cpu_arm7tdmi_switch_mm)
  * cpu_arm7tdmi_proc_fin()
  */
 ENTRY(cpu_arm7tdmi_proc_fin)
-               mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-               msr     cpsr_c, r0
                mov     pc, lr
 
 /*

diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 8be81992645d8d814517510ea473d85c604888bd..86f80aa56216b8ecf3159c090a83eeb2da372820 100644 (file)
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -69,19 +69,11 @@ ENTRY(cpu_arm920_proc_init)
  * cpu_arm920_proc_fin()
  */
 ENTRY(cpu_arm920_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
-       bl      arm920_flush_kern_cache_all
-#else
-       bl      v4wt_flush_kern_cache_all
-#endif
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm920_reset(loc)

diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index c0ff8e4b1074bac560f318a25c2715b89976c603..f76ce9b62883be61a1abe9baf67ae1a4ca4d8324 100644 (file)
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -71,19 +71,11 @@ ENTRY(cpu_arm922_proc_init)
  * cpu_arm922_proc_fin()
  */
 ENTRY(cpu_arm922_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
-       bl      arm922_flush_kern_cache_all
-#else
-       bl      v4wt_flush_kern_cache_all
-#endif
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm922_reset(loc)

diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 3c6cffe400f685f4dc3e32ccf078ef726d88d625..657bd3f7c153bf033f704636a323339129bb5d11 100644 (file)
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -92,15 +92,11 @@ ENTRY(cpu_arm925_proc_init)
  * cpu_arm925_proc_fin()
  */
 ENTRY(cpu_arm925_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm925_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm925_reset(loc)

diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 75b707c9cce1ad31c2adf960d99e99cb5a266f8d..73f1f3c689108fcade13d8dbb26e057105247645 100644 (file)
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -61,15 +61,11 @@ ENTRY(cpu_arm926_proc_init)
  * cpu_arm926_proc_fin()
  */
 ENTRY(cpu_arm926_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm926_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm926_reset(loc)

diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 1af1657819eb8e32caf40dbbc148ca2c0259144f..fffb061a45a558ee8dc5883dcba4a0e64ef53311 100644 (file)
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -37,15 +37,11 @@ ENTRY(cpu_arm940_switch_mm)
  * cpu_arm940_proc_fin()
  */
 ENTRY(cpu_arm940_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm940_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x00001000             @ i-cache
        bic     r0, r0, #0x00000004             @ d-cache
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm940_reset(loc)

diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 1664b6aaff794957723cfac21696e8a2af030f3b..249a6053760a357baa0dca13c3d67bf49ebf975e 100644 (file)
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -44,15 +44,11 @@ ENTRY(cpu_arm946_switch_mm)
  * cpu_arm946_proc_fin()
  */
 ENTRY(cpu_arm946_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      arm946_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x00001000             @ i-cache
        bic     r0, r0, #0x00000004             @ d-cache
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_arm946_reset(loc)

diff --git a/arch/arm/mm/proc-arm9tdmi.S b/arch/arm/mm/proc-arm9tdmi.S
index 28545c29dbcda317db178a564a7a894f3a846f96..db475667fac2c95df3ab30fdabda084eab94c3f3 100644 (file)
--- a/arch/arm/mm/proc-arm9tdmi.S
+++ b/arch/arm/mm/proc-arm9tdmi.S
@@ -36,8 +36,6 @@ ENTRY(cpu_arm9tdmi_switch_mm)
  * cpu_arm9tdmi_proc_fin()
  */
 ENTRY(cpu_arm9tdmi_proc_fin)
-               mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-               msr     cpsr_c, r0
                mov     pc, lr
 
 /*

diff --git a/arch/arm/mm/proc-fa526.S b/arch/arm/mm/proc-fa526.S
index 08f5ac237ad4e83e67b7540a9680d28c619edc41..7803fdf7002933da8e63a3383f9da818ecea724c 100644 (file)
--- a/arch/arm/mm/proc-fa526.S
+++ b/arch/arm/mm/proc-fa526.S
@@ -39,17 +39,13 @@ ENTRY(cpu_fa526_proc_init)
  * cpu_fa526_proc_fin()
  */
 ENTRY(cpu_fa526_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      fa_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
        nop
        nop
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_fa526_reset(loc)

diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index 53e63234384992ed07daf2eb48da91eaa5fa4a7d..b304d0104a4ef9c240191e42b7e08460706408b8 100644 (file)
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -75,11 +75,6 @@ ENTRY(cpu_feroceon_proc_init)
  * cpu_feroceon_proc_fin()
  */
 ENTRY(cpu_feroceon_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      feroceon_flush_kern_cache_all
-
 #if defined(CONFIG_CACHE_FEROCEON_L2) && \
        !defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
        mov     r0, #0
@@ -91,7 +86,7 @@ ENTRY(cpu_feroceon_proc_fin)
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_feroceon_reset(loc)

diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index caa31154e7dbf71417beebc71128e0d061fb17ce..5f6892fcc1671f28070f175bc6eeda03bbe614c5 100644 (file)
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -51,15 +51,11 @@ ENTRY(cpu_mohawk_proc_init)
  * cpu_mohawk_proc_fin()
  */
 ENTRY(cpu_mohawk_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      mohawk_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1800                 @ ...iz...........
        bic     r0, r0, #0x0006                 @ .............ca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_mohawk_reset(loc)

diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index 7b706b38990625c08ca3595ff19b6657fcbb0648..a201eb04b5e1a6327d1a5375c00b669ee7fc439c 100644 (file)
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -44,17 +44,13 @@ ENTRY(cpu_sa110_proc_init)
  * cpu_sa110_proc_fin()
  */
 ENTRY(cpu_sa110_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      v4wb_flush_kern_cache_all       @ clean caches
-1:     mov     r0, #0
+       mov     r0, #0
        mcr     p15, 0, r0, c15, c2, 2          @ Disable clock switching
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_sa110_reset(loc)

diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 5c47760c206437c0fbe7219aebae464b19929c7b..7ddc4805bf97a6fe722f54b3a769974bfaa42a1b 100644 (file)
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -55,16 +55,12 @@ ENTRY(cpu_sa1100_proc_init)
  *  - Clean and turn off caches.
  */
 ENTRY(cpu_sa1100_proc_fin)
-       stmfd   sp!, {lr}
-       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
-       msr     cpsr_c, ip
-       bl      v4wb_flush_kern_cache_all
        mcr     p15, 0, ip, c15, c2, 2          @ Disable clock switching
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  * cpu_sa1100_reset(loc)

diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 2f5a3c23a0fe0cedf2ba349d5224e58f03e5702a..22aac85151966d3058ace5cdb24eb4a608605e16 100644 (file)
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -42,14 +42,11 @@ ENTRY(cpu_v6_proc_init)
        mov     pc, lr
 
 ENTRY(cpu_v6_proc_fin)
-       stmfd   sp!, {lr}
-       cpsid   if                              @ disable interrupts
-       bl      v6_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x0006                 @ .............ca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 
 /*
  *     cpu_v6_reset(loc)

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 8071bcd4c9957ce6ac2146573677ac6767dfbaae..6a8506d99ee9abbb0845f39d94d663f802c56885 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -45,14 +45,11 @@ ENTRY(cpu_v7_proc_init)
 ENDPROC(cpu_v7_proc_init)
 
 ENTRY(cpu_v7_proc_fin)
-       stmfd   sp!, {lr}
-       cpsid   if                              @ disable interrupts
-       bl      v7_flush_kern_cache_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x0006                 @ .............ca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldmfd   sp!, {pc}
+       mov     pc, lr
 ENDPROC(cpu_v7_proc_fin)
 
 /*

diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index e5797f1c1db7d0dd4ccf06ff308655be1d2aa2a9..361a51e4903063ffc82f6831f3bee47e3a957860 100644 (file)
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -90,15 +90,11 @@ ENTRY(cpu_xsc3_proc_init)
  * cpu_xsc3_proc_fin()
  */
 ENTRY(cpu_xsc3_proc_fin)
-       str     lr, [sp, #-4]!
-       mov     r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
-       msr     cpsr_c, r0
-       bl      xsc3_flush_kern_cache_all       @ clean caches
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1800                 @ ...IZ...........
        bic     r0, r0, #0x0006                 @ .............CA.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldr     pc, [sp], #4
+       mov     pc, lr
 
 /*
  * cpu_xsc3_reset(loc)

diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 63037e2162f201ba76ad34604c2cd09ab450d71b..14075979bcbac1a4bfe7ae346e97058de819d448 100644 (file)
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -124,15 +124,11 @@ ENTRY(cpu_xscale_proc_init)
  * cpu_xscale_proc_fin()
  */
 ENTRY(cpu_xscale_proc_fin)
-       str     lr, [sp, #-4]!
-       mov     r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
-       msr     cpsr_c, r0
-       bl      xscale_flush_kern_cache_all     @ clean caches
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1800                 @ ...IZ...........
        bic     r0, r0, #0x0006                 @ .............CA.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
-       ldr     pc, [sp], #4
+       mov     pc, lr
 
 /*
  * cpu_xscale_reset(loc)