drm/amd/display: add two lane settings training options

[why]
option 1: disallow different lanes to have different lane settings
option 2: dpcd lane settings will always use the same hw lane settings
even if it doesn't match requested lane adjust

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 9c956fe69b614c692ba8ce85f8b1f645e5e54a12..4b89a2727c1caf58ec4e70ef34a8f38ff1751a21 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -737,8 +737,17 @@ void dp_decide_lane_settings(
 
        /* we find the maximum of the requested settings across all lanes*/
        /* and set this maximum for all lanes*/
-       maximize_lane_settings(lt_settings, hw_lane_settings);
        dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings);
+
+       if (lt_settings->disallow_per_lane_settings) {
+               /* we find the maximum of the requested settings across all lanes*/
+               /* and set this maximum for all lanes*/
+               maximize_lane_settings(lt_settings, hw_lane_settings);
+
+               if (lt_settings->always_match_dpcd_with_hw_lane_settings)
+                       dp_hw_to_dpcd_lane_settings(lt_settings, hw_lane_settings, dpcd_lane_settings);
+       }
+
 }
 
 static uint8_t get_nibble_at_index(const uint8_t *buf,
@@ -1453,6 +1462,8 @@ static inline void decide_8b_10b_training_settings(
        lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);
        lt_settings->enhanced_framing = 1;
        lt_settings->should_set_fec_ready = true;
+       lt_settings->disallow_per_lane_settings = true;
+       lt_settings->always_match_dpcd_with_hw_lane_settings = true;
        dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
 }
 
@@ -1479,6 +1490,7 @@ static inline void decide_128b_132b_training_settings(struct dc_link *link,
                        link->dpcd_caps.lttpr_caps.phy_repeater_cnt) + 1) * 20000;
        lt_settings->lttpr_mode = dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) ?
                        LTTPR_MODE_NON_TRANSPARENT : LTTPR_MODE_TRANSPARENT;
+       lt_settings->disallow_per_lane_settings = true;
        dp_hw_to_dpcd_lane_settings(lt_settings,
                        lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
 }

diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h
index 622c03f15df237954a9ed217746178817a186fa5..424bccd364340fa31f3bc255802fda95e43c6572 100644 (file)
--- a/drivers/gpu/drm/amd/display/include/link_service_types.h
+++ b/drivers/gpu/drm/amd/display/include/link_service_types.h
@@ -118,7 +118,6 @@ struct link_training_settings {
 #endif
 
        bool enhanced_framing;
-       bool allow_invalid_msa_timing_param;
        enum lttpr_mode lttpr_mode;
 
        /* disallow different lanes to have different lane settings */