arm64: dts: st: add power domain on stm32mp25

Add power domains on STM32MP25x SoC for supported low power modes:
- CPU_PD0/1: domain for idle of each core Cortex A35 (CStop)
- CLUSTER_PD: D1 domain with Stop1 and LP-Stop1 modes support when
  the Cortex A35 cluster and each device assigned to CPU1=CA35
  are deactivated
- RET_PD: D1 domain retention (VDDCore is reduced) to support
          the LPLV-Stop1 mode

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index 2013f391f4b952fd50c8fc9d9c759ffc8ae7f5c7..96d6de29c14c736991bf231748937aa0974f91f7 100644 (file)
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -20,6 +20,8 @@
                        device_type = "cpu";
                        reg = <0>;
                        enable-method = "psci";
+                       power-domains = <&CPU_PD0>;
+                       power-domain-names = "psci";
                };
        };
 
@@ -90,6 +92,20 @@
        psci {
                compatible = "arm,psci-1.0";
                method = "smc";
+
+               CPU_PD0: power-domain-cpu0 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+               };
+
+               CLUSTER_PD: power-domain-cluster {
+                       #power-domain-cells = <0>;
+                       power-domains = <&RET_PD>;
+               };
+
+               RET_PD: power-domain-retention {
+                       #power-domain-cells = <0>;
+               };
        };
 
        timer {

diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi
index 69001f924d17c677b130624efb1734921aff4a6c..652e41facb35ebd5e0f4becd9c97f5de832088e1 100644 (file)
--- a/arch/arm64/boot/dts/st/stm32mp253.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi
@@ -12,6 +12,8 @@
                        device_type = "cpu";
                        reg = <1>;
                        enable-method = "psci";
+                       power-domains = <&CPU_PD1>;
+                       power-domain-names = "psci";
                };
        };
 
@@ -21,6 +23,13 @@
                interrupt-affinity = <&cpu0>, <&cpu1>;
        };
 
+       psci {
+               CPU_PD1: power-domain-cpu1 {
+                       #power-domain-cells = <0>;
+                       power-domains = <&CLUSTER_PD>;
+               };
+       };
+
        timer {
                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,