ARM: dts: qcom: sdx65: Add support for PCIe EP

Add support for PCIe Endpoint controller on the
Qualcomm SDX65 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1684432073-28490-4-git-send-email-quic_rohiagar@quicinc.com

diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 2fe61c296e392f60687512cfae63bcc598e3fa86..1a3583029a649e1bdb705f969bf60d8f781dac1f 100644 (file)
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -295,6 +296,56 @@
                        status = "disabled";
                };
 
+               pcie_ep: pcie-ep@1c00000 {
+                       compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep";
+                       reg = <0x01c00000 0x3000>,
+                             <0x40000000 0xf1d>,
+                             <0x40000f20 0xa8>,
+                             <0x40001000 0x1000>,
+                             <0x40200000 0x100000>,
+                             <0x01c03000 0x3000>;
+                       reg-names = "parf",
+                                   "dbi",
+                                   "elbi",
+                                   "atu",
+                                   "addr_space",
+                                   "mmio";
+
+                       qcom,perst-regs = <&tcsr 0xb258 0xb270>;
+
+                       clocks = <&gcc GCC_PCIE_AUX_CLK>,
+                                <&gcc GCC_PCIE_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_MSTR_AXI_CLK>,
+                                <&gcc GCC_PCIE_SLV_AXI_CLK>,
+                                <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
+                                <&gcc GCC_PCIE_SLEEP_CLK>,
+                                <&gcc GCC_PCIE_0_CLKREF_EN>;
+                       clock-names = "aux",
+                                     "cfg",
+                                     "bus_master",
+                                     "bus_slave",
+                                     "slave_q2a",
+                                     "sleep",
+                                     "ref";
+
+                       interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "global", "doorbell";
+
+                       resets = <&gcc GCC_PCIE_BCR>;
+                       reset-names = "core";
+
+                       power-domains = <&gcc PCIE_GDSC>;
+
+                       phys = <&pcie_phy>;
+                       phy-names = "pcie-phy";
+
+                       max-link-speed = <3>;
+                       num-lanes = <2>;
+
+                       status = "disabled";
+               };
+
                pcie_phy: phy@1c06000 {
                        compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy";
                        reg = <0x01c06000 0x2000>;
@@ -332,6 +383,11 @@
                        #hwlock-cells = <1>;
                };
 
+               tcsr: syscon@1fcb000 {
+                       compatible = "qcom,sdx65-tcsr", "syscon";
+                       reg = <0x01fc0000 0x1000>;
+               };
+
                ipa: ipa@3f40000 {
                        compatible = "qcom,sdx65-ipa";