return container_of(output, struct tegra_dsi, output);
 }
 
-static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi,
-                                           unsigned long reg)
+static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned long reg)
 {
        return readl(dsi->regs + (reg << 2));
 }
 
-static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value,
+static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
                                    unsigned long reg)
 {
        writel(value, dsi->regs + (reg << 2));
        struct tegra_dsi *dsi = node->info_ent->data;
 
 #define DUMP_REG(name)                                         \
-       seq_printf(s, "%-32s %#05x %08lx\n", #name, name,       \
+       seq_printf(s, "%-32s %#05x %08x\n", #name, name,        \
                   tegra_dsi_readl(dsi, name))
 
        DUMP_REG(DSI_INCR_SYNCPT);
 static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
 {
        struct mipi_dphy_timing timing;
-       unsigned long value, period;
+       unsigned long period;
+       u32 value;
        long rate;
        int err;
 
 {
        struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
        struct tegra_dsi *dsi = to_dsi(output);
-       unsigned long value;
+       u32 value;
        int err;
 
        if (!dsi->enabled)
 
 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
 {
-       unsigned long value;
+       u32 value;
 
        value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
        tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);