drm/amd/display: use previous aux timeout val if no repeater.

[Why]
The aux timeout value is not default before reading link cap.
Setting it to default when lttpr is not enabled causes some monitor
not to light up.

[How]
Read the aux engine timeout value before setting it to extended.
Set the aux engine timeout to its previous value if no lttpr.

Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index a2e6adacaff66548a9fa2dac72b40d7f1358560f..c8037af93e0a0a124343ea9db84110c46db58cdf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -650,17 +650,16 @@ bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
 }
 
 
-enum dc_status dc_link_aux_configure_timeout(struct ddc_service *ddc,
+uint32_t dc_link_aux_configure_timeout(struct ddc_service *ddc,
                uint32_t timeout)
 {
-       enum dc_status status = DC_OK;
+       uint32_t prev_timeout = 0;
        struct ddc *ddc_pin = ddc->ddc_pin;
 
-       if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout == NULL)
-               return DC_ERROR_UNEXPECTED;
-       if (!ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout))
-               status = DC_ERROR_UNEXPECTED;
-       return status;
+       if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout)
+               prev_timeout =
+                               ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);
+       return prev_timeout;
 }
 
 /*test only function*/

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 11b6e14b345e39ecc98dd96196375bc1b8847cae..6e1f00ab664676b42779688a702b82d786babb0d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -2977,6 +2977,7 @@ static bool retrieve_link_cap(struct dc_link *link)
        union dp_downstream_port_present ds_port = { 0 };
        enum dc_status status = DC_ERROR_UNEXPECTED;
        uint32_t read_dpcd_retry_cnt = 3;
+       uint32_t prev_timeout_val;
        int i;
        struct dp_sink_hw_fw_revision dp_hw_fw_revision;
 
@@ -2987,7 +2988,9 @@ static bool retrieve_link_cap(struct dc_link *link)
        link->is_lttpr_mode_transparent = true;
 
        if (ext_timeout_support) {
-               status = dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
+               prev_timeout_val =
+                               dc_link_aux_configure_timeout(link->ddc,
+                                               LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD);
        }
 
        memset(dpcd_data, '\0', sizeof(dpcd_data));
@@ -3022,7 +3025,7 @@ static bool retrieve_link_cap(struct dc_link *link)
                return false;
        }
 
-       if (ext_timeout_support && link->dpcd_caps.dpcd_rev.raw >= 0x14) {
+       if (ext_timeout_support) {
                status = core_link_read_dpcd(
                                link,
                                DP_PHY_REPEATER_CNT,
@@ -3063,7 +3066,7 @@ static bool retrieve_link_cap(struct dc_link *link)
                                        &link->dpcd_caps.lttpr_caps.max_ext_timeout,
                                        sizeof(link->dpcd_caps.lttpr_caps.max_ext_timeout));
                } else {
-                       dc_link_aux_configure_timeout(link->ddc, LINK_AUX_DEFAULT_TIMEOUT_PERIOD);
+                       dc_link_aux_configure_timeout(link->ddc, prev_timeout_val);
                }
        }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index e472608faf3351ba112a1968792be6f6e4aa207a..f7626cd70ec83ed32b91e337c7d05afccbaa3e05 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -60,12 +60,14 @@ enum {
        AUX_DEFER_RETRY_COUNTER = 6
 };
 
-#define TIME_OUT_INCREMENT      1016
-#define TIME_OUT_MULTIPLIER_8  8
-#define TIME_OUT_MULTIPLIER_16  16
-#define TIME_OUT_MULTIPLIER_32  32
-#define TIME_OUT_MULTIPLIER_64  64
-#define MAX_TIMEOUT_LENGTH      127
+#define TIME_OUT_INCREMENT        1016
+#define TIME_OUT_MULTIPLIER_8     8
+#define TIME_OUT_MULTIPLIER_16    16
+#define TIME_OUT_MULTIPLIER_32    32
+#define TIME_OUT_MULTIPLIER_64    64
+#define MAX_TIMEOUT_LENGTH        127
+#define DEFAULT_AUX_ENGINE_MULT   0
+#define DEFAULT_AUX_ENGINE_LENGTH 69
 
 static void release_engine(
        struct dce_aux *engine)
@@ -427,11 +429,14 @@ void dce110_engine_destroy(struct dce_aux **engine)
 
 }
 
-static bool dce_aux_configure_timeout(struct ddc_service *ddc,
+static uint32_t dce_aux_configure_timeout(struct ddc_service *ddc,
                uint32_t timeout_in_us)
 {
        uint32_t multiplier = 0;
        uint32_t length = 0;
+       uint32_t prev_length = 0;
+       uint32_t prev_mult = 0;
+       uint32_t prev_timeout_val = 0;
        struct ddc *ddc_pin = ddc->ddc_pin;
        struct dce_aux *aux_engine = ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
        struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
@@ -440,7 +445,10 @@ static bool dce_aux_configure_timeout(struct ddc_service *ddc,
        aux110->polling_timeout_period = timeout_in_us * SW_AUX_TIMEOUT_PERIOD_MULTIPLIER;
 
        /* 2-Update aux timeout period length and multiplier */
-       if (timeout_in_us <= TIME_OUT_INCREMENT) {
+       if (timeout_in_us == 0) {
+               multiplier = DEFAULT_AUX_ENGINE_MULT;
+               length = DEFAULT_AUX_ENGINE_LENGTH;
+       } else if (timeout_in_us <= TIME_OUT_INCREMENT) {
                multiplier = 0;
                length = timeout_in_us/TIME_OUT_MULTIPLIER_8;
                if (timeout_in_us % TIME_OUT_MULTIPLIER_8 != 0)
@@ -464,9 +472,29 @@ static bool dce_aux_configure_timeout(struct ddc_service *ddc,
 
        length = (length < MAX_TIMEOUT_LENGTH) ? length : MAX_TIMEOUT_LENGTH;
 
+       REG_GET_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, &prev_length, AUX_RX_TIMEOUT_LEN_MUL, &prev_mult);
+
+       switch (prev_mult) {
+       case 0:
+               prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_8;
+               break;
+       case 1:
+               prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_16;
+               break;
+       case 2:
+               prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_32;
+               break;
+       case 3:
+               prev_timeout_val = prev_length * TIME_OUT_MULTIPLIER_64;
+               break;
+       default:
+               prev_timeout_val = DEFAULT_AUX_ENGINE_LENGTH * TIME_OUT_MULTIPLIER_8;
+               break;
+       }
+
        REG_UPDATE_SEQ_2(AUX_DPHY_RX_CONTROL1, AUX_RX_TIMEOUT_LEN, length, AUX_RX_TIMEOUT_LEN_MUL, multiplier);
 
-       return true;
+       return prev_timeout_val;
 }
 
 static struct dce_aux_funcs aux_functions = {

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
index b4b2c79a80736351b6faac766381316f8d2d913c..2e2e925a506ba861915a708e593603e1d4ca704a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
@@ -311,7 +311,7 @@ bool dce_aux_transfer_with_retries(struct ddc_service *ddc,
                struct aux_payload *cmd);
 
 struct dce_aux_funcs {
-       bool (*configure_timeout)
+       uint32_t (*configure_timeout)
                (struct ddc_service *ddc,
                 uint32_t timeout);
        void (*destroy)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
index 14716ba3566257458767a2b41349f3c4ac4060f1..de2d160114db7f696989c646f4490b3ea48c2e95 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_ddc.h
@@ -105,7 +105,7 @@ int dc_link_aux_transfer_raw(struct ddc_service *ddc,
 bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
                struct aux_payload *payload);
 
-enum dc_status dc_link_aux_configure_timeout(struct ddc_service *ddc,
+uint32_t dc_link_aux_configure_timeout(struct ddc_service *ddc,
                uint32_t timeout);
 
 void dal_ddc_service_write_scdc_data(

diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
index 045138dbdccb471989f8215defcabe18829b376a..a6500b98fe0d916a2aec84d245a80726b9e0176e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h
@@ -28,7 +28,7 @@
 
 #define LINK_TRAINING_ATTEMPTS 4
 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
-#define LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD 32000 /*us*/
+#define LINK_AUX_DEFAULT_EXTENDED_TIMEOUT_PERIOD 3200 /*us*/
 #define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 400 /*us*/
 
 struct dc_link;