c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 
        if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
-               dev_warn(dev->dev, "unable to set dbbuf\n");
+               dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
                /* Free memory and continue on */
                nvme_dbbuf_dma_free(dev);
        }
        result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
                                      &pci_status);
        if (result == PCIBIOS_SUCCESSFUL)
-               dev_warn(dev->dev,
+               dev_warn(dev->ctrl.device,
                         "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
                         csts, pci_status);
        else
-               dev_warn(dev->dev,
+               dev_warn(dev->ctrl.device,
                         "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
                         csts, result);
 }
         */
        if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
                dev->q_depth = 2;
-               dev_warn(dev->dev, "detected Apple NVMe controller, set "
-                       "queue depth=%u to work around controller resets\n",
+               dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
+                       "set queue depth=%u to work around controller resets\n",
                        dev->q_depth);
        }
 
                if (dev->cmbsz) {
                        if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
                                                    &dev_attr_cmb.attr, NULL))
-                               dev_warn(dev->dev,
+                               dev_warn(dev->ctrl.device,
                                         "failed to add sysfs attribute for CMB\n");
                }
        }