u8 *in, const u8 *out, unsigned int xfer_len,
                               unsigned int *actual_len, bool continued)
 {
+       int retry = 2;
        u32 reg;
        int ret;
 
        /* clean SVC_I3C_MINT_IBIWON w1c bits */
        writel(SVC_I3C_MINT_IBIWON, master->regs + SVC_I3C_MSTATUS);
 
-       writel(SVC_I3C_MCTRL_REQUEST_START_ADDR |
-              xfer_type |
-              SVC_I3C_MCTRL_IBIRESP_NACK |
-              SVC_I3C_MCTRL_DIR(rnw) |
-              SVC_I3C_MCTRL_ADDR(addr) |
-              SVC_I3C_MCTRL_RDTERM(*actual_len),
-              master->regs + SVC_I3C_MCTRL);
 
-       ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
+       while (retry--) {
+               writel(SVC_I3C_MCTRL_REQUEST_START_ADDR |
+                      xfer_type |
+                      SVC_I3C_MCTRL_IBIRESP_NACK |
+                      SVC_I3C_MCTRL_DIR(rnw) |
+                      SVC_I3C_MCTRL_ADDR(addr) |
+                      SVC_I3C_MCTRL_RDTERM(*actual_len),
+                      master->regs + SVC_I3C_MCTRL);
+
+               ret = readl_poll_timeout(master->regs + SVC_I3C_MSTATUS, reg,
                                 SVC_I3C_MSTATUS_MCTRLDONE(reg), 0, 1000);
-       if (ret)
-               goto emit_stop;
+               if (ret)
+                       goto emit_stop;
 
-       if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) {
-               ret = -ENXIO;
-               *actual_len = 0;
-               goto emit_stop;
+               if (readl(master->regs + SVC_I3C_MERRWARN) & SVC_I3C_MERRWARN_NACK) {
+                       /*
+                        * According to I3C Spec 1.1.1, 11-Jun-2021, section: 5.1.2.2.3.
+                        * If the Controller chooses to start an I3C Message with an I3C Dynamic
+                        * Address, then special provisions shall be made because that same I3C
+                        * Target may be initiating an IBI or a Controller Role Request. So, one of
+                        * three things may happen: (skip 1, 2)
+                        *
+                        * 3. The Addresses match and the RnW bits also match, and so neither
+                        * Controller nor Target will ACK since both are expecting the other side to
+                        * provide ACK. As a result, each side might think it had "won" arbitration,
+                        * but neither side would continue, as each would subsequently see that the
+                        * other did not provide ACK.
+                        * ...
+                        * For either value of RnW: Due to the NACK, the Controller shall defer the
+                        * Private Write or Private Read, and should typically transmit the Target
+                        * Address again after a Repeated START (i.e., the next one or any one prior
+                        * to a STOP in the Frame). Since the Address Header following a Repeated
+                        * START is not arbitrated, the Controller will always win (see Section
+                        * 5.1.2.2.4).
+                        */
+                       if (retry && addr != 0x7e) {
+                               writel(SVC_I3C_MERRWARN_NACK, master->regs + SVC_I3C_MERRWARN);
+                       } else {
+                               ret = -ENXIO;
+                               *actual_len = 0;
+                               goto emit_stop;
+                       }
+               } else {
+                       break;
+               }
        }
 
        /*