PCI: Add Precision Time Measurement (PTM) support

Add Precision Time Measurement (PTM) support (see PCIe r3.1, sec 6.22).

Enable PTM on PTM Root devices and switch ports.  This does not enable PTM
on endpoints.

There currently are no PTM-capable devices on the market, but it is
expected to be supported by the Intel Apollo Lake platform.

[bhelgaas: complete rework]
Signed-off-by: Jonathan Yong <jonathan.yong@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 9730c474b0163ccab1d9aa8027cf1c00d6ca823a..194521bfb1a3561226874f5ed4b985f4c6f18786 100644 (file)
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -332,6 +332,12 @@ static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
 
 void pci_enable_acs(struct pci_dev *dev);
 
+#ifdef CONFIG_PCIE_PTM
+void pci_ptm_init(struct pci_dev *dev);
+#else
+static inline void pci_ptm_init(struct pci_dev *dev) { }
+#endif
+
 struct pci_dev_reset_methods {
        u16 vendor;
        u16 device;

diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig
index 7fcea75afa4cf9a3b702c2773ead13c75a65de80..7ce77635e5ad229667f5a256aea7e3e4b22de390 100644 (file)
--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
@@ -92,3 +92,14 @@ config PCIE_DPC
          will be handled by the DPC driver.  If your system doesn't
          have this capability or you do not want to use this feature,
          it is safe to answer N.
+
+config PCIE_PTM
+       bool "PCIe Precision Time Measurement support"
+       default n
+       depends on PCIEPORTBUS
+       help
+         This enables PCI Express Precision Time Measurement (PTM)
+         support.
+
+         This is only useful if you have devices that support PTM, but it
+         is safe to enable even if you don't.

diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile
index b24525b3dec1a8833f76c9d5ef491357ebf8a6cf..36e35ea8fde7198ccc69b831eb6004131de50709 100644 (file)
--- a/drivers/pci/pcie/Makefile
+++ b/drivers/pci/pcie/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_PCIEAER)         += aer/
 obj-$(CONFIG_PCIE_PME) += pme.o
 
 obj-$(CONFIG_PCIE_DPC) += pcie-dpc.o
+obj-$(CONFIG_PCIE_PTM) += ptm.o

diff --git a/drivers/pci/pcie/ptm.c b/drivers/pci/pcie/ptm.c
new file mode 100644 (file)
index 0000000..48eea4e
--- /dev/null
+++ b/drivers/pci/pcie/ptm.c
@@ -0,0 +1,70 @@
+/*
+ * PCI Express Precision Time Measurement
+ * Copyright (c) 2016, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include "../pci.h"
+
+static void pci_ptm_info(struct pci_dev *dev)
+{
+       dev_info(&dev->dev, "PTM enabled%s\n", dev->ptm_root ? " (root)" : "");
+}
+
+void pci_ptm_init(struct pci_dev *dev)
+{
+       int pos;
+       u32 cap, ctrl;
+       struct pci_dev *ups;
+
+       if (!pci_is_pcie(dev))
+               return;
+
+       pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
+       if (!pos)
+               return;
+
+       /*
+        * Enable PTM only on interior devices (root ports, switch ports,
+        * etc.) on the assumption that it causes no link traffic until an
+        * endpoint enables it.
+        */
+       if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT ||
+            pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END))
+               return;
+
+       pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
+
+       /*
+        * There's no point in enabling PTM unless it's enabled in the
+        * upstream device or this device can be a PTM Root itself.  Per
+        * the spec recommendation (PCIe r3.1, sec 7.32.3), select the
+        * furthest upstream Time Source as the PTM Root.
+        */
+       ups = pci_upstream_bridge(dev);
+       if (ups && ups->ptm_enabled) {
+               ctrl = PCI_PTM_CTRL_ENABLE;
+       } else {
+               if (cap & PCI_PTM_CAP_ROOT) {
+                       ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT;
+                       dev->ptm_root = 1;
+               } else
+                       return;
+       }
+
+       pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
+       dev->ptm_enabled = 1;
+
+       pci_ptm_info(dev);
+}

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 93f280df342824fd89c5206f99ff2733fd7e7044..e2e4244720588e462860c00f38c6ac74c2ff549b 100644 (file)
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1667,6 +1667,9 @@ static void pci_init_capabilities(struct pci_dev *dev)
        pci_enable_acs(dev);
 
        pci_cleanup_aer_error_status_regs(dev);
+
+       /* Precision Time Measurement */
+       pci_ptm_init(dev);
 }
 
 /*

diff --git a/include/linux/pci.h b/include/linux/pci.h
index 2599a980340f44f2550bacded406cb34f38808dc..96c509fa9d46d6cc851bd396767679619906bf37 100644 (file)
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -367,6 +367,11 @@ struct pci_dev {
        int rom_attr_enabled;           /* has display of the rom attribute been enabled? */
        struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
        struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
+
+#ifdef CONFIG_PCIE_PTM
+       unsigned int    ptm_root:1;
+       unsigned int    ptm_enabled:1;
+#endif
 #ifdef CONFIG_PCI_MSI
        const struct attribute_group **msi_irq_groups;
 #endif

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 404095124ae203c7d8ca0e4e206416368af39cb5..926fff41b417f42248f2aa98180762940c815249 100644 (file)
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -671,7 +671,8 @@
 #define PCI_EXT_CAP_ID_PMUX    0x1A    /* Protocol Multiplexing */
 #define PCI_EXT_CAP_ID_PASID   0x1B    /* Process Address Space ID */
 #define PCI_EXT_CAP_ID_DPC     0x1D    /* Downstream Port Containment */
-#define PCI_EXT_CAP_ID_MAX     PCI_EXT_CAP_ID_DPC
+#define PCI_EXT_CAP_ID_PTM     0x1F    /* Precision Time Measurement */
+#define PCI_EXT_CAP_ID_MAX     PCI_EXT_CAP_ID_PTM
 
 #define PCI_EXT_CAP_DSN_SIZEOF 12
 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
@@ -964,4 +965,11 @@
 
 #define PCI_EXP_DPC_SOURCE_ID          10      /* DPC Source Identifier */
 
+/* Precision Time Measurement */
+#define PCI_PTM_CAP                    0x04        /* PTM Capability */
+#define  PCI_PTM_CAP_ROOT              0x00000004  /* Root capable */
+#define PCI_PTM_CTRL                   0x08        /* PTM Control */
+#define  PCI_PTM_CTRL_ENABLE           0x00000001  /* PTM enable */
+#define  PCI_PTM_CTRL_ROOT             0x00000002  /* Root select */
+
 #endif /* LINUX_PCI_REGS_H */