drm/radeon: only print meaningful VM faults

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index dcd4518a9b087edbab07ab96f58d0d0658b5a23c..0b2471107137a90af6677ece89a7351c9b97f599 100644 (file)
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -7676,14 +7676,16 @@ restart_ih:
                        addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
                        status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
                        mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
+                       /* reset addr and status */
+                       WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
+                       if (addr == 0x0 && status == 0x0)
+                               break;
                        dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
                        dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
                                addr);
                        dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
                                status);
                        cik_vm_decode_fault(rdev, status, addr, mc_client);
-                       /* reset addr and status */
-                       WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
                        break;
                case 167: /* VCE */
                        DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data);

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e2f605224e8c701e9b0eceb138ee77da443f51ee..d5d4d3a86731aec88e5221042911b593bc20fa7a 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -5066,14 +5066,16 @@ restart_ih:
                case 147:
                        addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
                        status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
+                       /* reset addr and status */
+                       WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
+                       if (addr == 0x0 && status == 0x0)
+                               break;
                        dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
                        dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
                                addr);
                        dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
                                status);
                        cayman_vm_decode_fault(rdev, status, addr);
-                       /* reset addr and status */
-                       WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
                        break;
                case 176: /* CP_INT in ring buffer */
                case 177: /* CP_INT in IB1 */

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 730cee2c34cffd33d44de32c4821ecdfa2fee99b..eba0225259a457a3d494f39bfee13af0cdc865e6 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -6376,14 +6376,16 @@ restart_ih:
                case 147:
                        addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
                        status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
+                       /* reset addr and status */
+                       WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
+                       if (addr == 0x0 && status == 0x0)
+                               break;
                        dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
                        dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
                                addr);
                        dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
                                status);
                        si_vm_decode_fault(rdev, status, addr);
-                       /* reset addr and status */
-                       WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
                        break;
                case 176: /* RINGID0 CP_INT */
                        radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);