drm/amd/display: Disable idle optimizations before programming DCN

[Why]
Programming DCN is explicitly forbidden during idle optimzations allowed
state. Existing implemenation relies on OS/DM, which is not robust. Instead
DC should sequence this.

Note that DC will not re-enter idle optimized state on its own, it is only
responsible for catching out of sequence calls. It is still DM
responsibility to sequence appropriate for optimized power, but this change
removes the requirement for DM to cover the .1% case.

[How]
 - elevate updates during idle optimized state to full updates
 - disable idle power optimizations prior to programming

Signed-off-by: Jun Lei <jun.lei@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index ef0b5941bc500cd6224ee26e463b040f1bdc716a..92eb1ca1634fcc7f32d4ab8606a556680e5ca9e6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1250,6 +1250,9 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c
        int i, k, l;
        struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+       dc_allow_idle_optimizations(dc, false);
+#endif
 
        for (i = 0; i < context->stream_count; i++)
                dc_streams[i] =  context->streams[i];
@@ -1838,6 +1841,11 @@ static enum surface_update_type check_update_surfaces_for_stream(
        int i;
        enum surface_update_type overall_type = UPDATE_TYPE_FAST;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+       if (dc->idle_optimizations_allowed)
+               overall_type = UPDATE_TYPE_FULL;
+
+#endif
        if (stream_status == NULL || stream_status->plane_count != surface_count)
                overall_type = UPDATE_TYPE_FULL;
 
@@ -2306,8 +2314,14 @@ static void commit_planes_for_stream(struct dc *dc,
                }
        }
 
-       if (update_type == UPDATE_TYPE_FULL && dc->optimize_seamless_boot_streams == 0) {
-               dc->hwss.prepare_bandwidth(dc, context);
+       if (update_type == UPDATE_TYPE_FULL) {
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+               dc_allow_idle_optimizations(dc, false);
+
+#endif
+               if (dc->optimize_seamless_boot_streams == 0)
+                       dc->hwss.prepare_bandwidth(dc, context);
+
                context_clock_trace(dc, context);
        }