arm64: dts: renesas: r8a779g0: Add PCIe Host and Endpoint nodes

Add PCIe Host and Endpoint nodes for R-Car V4H (R8A779G0).

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240822004454.1087582-2-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index c66a920060ff723030a432a1f958d4de6b254425..5498d3a8173dc77d11bf3c4ef6d00a0e821cf19d 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -175,6 +175,20 @@
                clock-frequency = <0>;
        };
 
+       pcie0_clkref: pcie0-clkref {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
+       pcie1_clkref: pcie1-clkref {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               /* This value must be overridden by the board */
+               clock-frequency = <0>;
+       };
+
        pmu_a76 {
                compatible = "arm,cortex-a76-pmu";
                interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
@@ -737,6 +751,126 @@
                        status = "disabled";
                };
 
+               pciec0: pcie@e65d0000 {
+                       compatible = "renesas,r8a779g0-pcie",
+                                    "renesas,rcar-gen4-pcie";
+                       reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>,
+                             <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
+                             <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
+                             <0 0xfe000000 0 0x400000>;
+                       reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
+                       interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi", "dma", "sft_ce", "app";
+                       clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
+                       clock-names = "core", "ref";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 624>;
+                       reset-names = "pwr";
+                       max-link-speed = <4>;
+                       num-lanes = <2>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       bus-range = <0x00 0xff>;
+                       device_type = "pci";
+                       ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>,
+                                <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>;
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
+                       snps,enable-cdm-check;
+                       status = "disabled";
+               };
+
+               pciec1: pcie@e65d8000 {
+                       compatible = "renesas,r8a779g0-pcie",
+                                    "renesas,rcar-gen4-pcie";
+                       reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>,
+                             <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
+                             <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
+                             <0 0xee900000 0 0x400000>;
+                       reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config";
+                       interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi", "dma", "sft_ce", "app";
+                       clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
+                       clock-names = "core", "ref";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 625>;
+                       reset-names = "pwr";
+                       max-link-speed = <4>;
+                       num-lanes = <2>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       bus-range = <0x00 0xff>;
+                       device_type = "pci";
+                       ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>,
+                                <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>;
+                       dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 2 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 3 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+                                       <0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
+                       snps,enable-cdm-check;
+                       status = "disabled";
+               };
+
+               pciec0_ep: pcie-ep@e65d0000 {
+                       compatible = "renesas,r8a779g0-pcie-ep",
+                                    "renesas,rcar-gen4-pcie-ep";
+                       reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>,
+                             <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>,
+                             <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>,
+                             <0 0xfe000000 0 0x400000>;
+                       reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
+                       interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "dma", "sft_ce", "app";
+                       clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>;
+                       clock-names = "core", "ref";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 624>;
+                       reset-names = "pwr";
+                       max-link-speed = <4>;
+                       num-lanes = <2>;
+                       max-functions = /bits/ 8 <2>;
+                       status = "disabled";
+               };
+
+               pciec1_ep: pcie-ep@e65d8000 {
+                       compatible = "renesas,r8a779g0-pcie-ep",
+                                    "renesas,rcar-gen4-pcie-ep";
+                       reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>,
+                             <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>,
+                             <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>,
+                             <0 0xee900000 0 0x400000>;
+                       reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space";
+                       interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "dma", "sft_ce", "app";
+                       clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>;
+                       clock-names = "core", "ref";
+                       power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
+                       resets = <&cpg 625>;
+                       reset-names = "pwr";
+                       max-link-speed = <4>;
+                       num-lanes = <2>;
+                       max-functions = /bits/ 8 <2>;
+                       status = "disabled";
+               };
+
                canfd: can@e6660000 {
                        compatible = "renesas,r8a779g0-canfd",
                                     "renesas,rcar-gen4-canfd";