]> www.infradead.org Git - users/borneoa/openocd-next.git/commitdiff
flash, target: avoid logging of numeric target state
authorTomas Vanek <vanekt@fbl.cz>
Sun, 18 May 2025 09:49:31 +0000 (11:49 +0200)
committerAntonio Borneo <borneo.antonio@gmail.com>
Sun, 25 May 2025 12:45:33 +0000 (12:45 +0000)
Replace it by target_state_name() helper.

Change-Id: I720f2bf121e6fd2c6987a7e8fa9e52593888ee6c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8918
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
src/flash/nor/ambiqmicro.c
src/target/espressif/esp32.c
src/target/espressif/esp32s2.c
src/target/espressif/esp32s3.c
src/target/stm8.c
src/target/xtensa/xtensa.c

index bb893778ce07d9a1c4763be8aef6bda69b923e67..67cc6b68a75c284036412c0fa61d28d242aaee7e 100644 (file)
@@ -309,9 +309,9 @@ static int ambiqmicro_exec_command(struct target *target,
                         */
                        target_poll(target);
                        alive_sleep(100);
-                       LOG_DEBUG("state = %d", target->state);
                } else {
-                       LOG_ERROR("Target not halted or running %d", target->state);
+                       LOG_ERROR("Target not halted or running (state is %s)",
+                                         target_state_name(target));
                        break;
                }
        }
index 399ba8e7cd7ef84e8966b3e184a24ed7a231c12a..5e2490a2297c20c444489ea610f9928cddcbef23 100644 (file)
@@ -192,8 +192,8 @@ static int esp32_soc_reset(struct target *target)
                alive_sleep(10);
                xtensa_poll(target);
                if (timeval_ms() >= timeout) {
-                       LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
-                               target->state);
+                       LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state %s",
+                               target_state_name(target));
                        get_timeout = true;
                        break;
                }
index b86e43e626c32eb252cceff9d303311dff94096c..e32893a6b21d5519f89cf2219ac274e7326df105 100644 (file)
@@ -272,8 +272,8 @@ static int esp32s2_soc_reset(struct target *target)
                alive_sleep(10);
                xtensa_poll(target);
                if (timeval_ms() >= timeout) {
-                       LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
-                               target->state);
+                       LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state %s",
+                               target_state_name(target));
                        return ERROR_TARGET_TIMEOUT;
                }
        }
index 82413f77fb0ccbf19ea0922ebc90ce54500f70a1..14f7a7bb64a767f8bfcc6ff92744397cccedcbae 100644 (file)
@@ -193,8 +193,8 @@ static int esp32s3_soc_reset(struct target *target)
                xtensa_poll(target);
                if (timeval_ms() >= timeout) {
                        LOG_TARGET_ERROR(target,
-                               "Timed out waiting for CPU to be reset, target state=%d",
-                               target->state);
+                               "Timed out waiting for CPU to be reset, target state %s",
+                               target_state_name(target));
                        get_timeout = true;
                        break;
                }
index 81c41f2b2a28da245fb1b22f6f4822da59a1f1c4..7785d40ef06c69cda9229b8aaee811078320f882 100644 (file)
@@ -870,7 +870,7 @@ static int stm8_poll(struct target *target)
        uint8_t csr1, csr2;
 
 #ifdef LOG_STM8
-       LOG_DEBUG("target->state=%d", target->state);
+       LOG_DEBUG("target->state %s", target_state_name(target));
 #endif
 
        /* read dm_csrx control regs */
index 3a877edfa6308de541075258f4e625b6100c9641..3366623d64a1f1ce81ed6fc5cafba7850fe3cc2b 100644 (file)
@@ -949,7 +949,8 @@ int xtensa_smpbreak_set(struct target *target, uint32_t set)
        xtensa->smp_break = set;
        if (target_was_examined(target))
                res = xtensa_smpbreak_write(xtensa, xtensa->smp_break);
-       LOG_TARGET_DEBUG(target, "set smpbreak=%" PRIx32 ", state=%i", set, target->state);
+       LOG_TARGET_DEBUG(target, "set smpbreak=%" PRIx32 ", state %s", set,
+                                        target_state_name(target));
        return res;
 }