Replace it by target_state_name() helper.
Change-Id: I720f2bf121e6fd2c6987a7e8fa9e52593888ee6c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8918
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
*/
target_poll(target);
alive_sleep(100);
- LOG_DEBUG("state = %d", target->state);
} else {
- LOG_ERROR("Target not halted or running %d", target->state);
+ LOG_ERROR("Target not halted or running (state is %s)",
+ target_state_name(target));
break;
}
}
alive_sleep(10);
xtensa_poll(target);
if (timeval_ms() >= timeout) {
- LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
- target->state);
+ LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state %s",
+ target_state_name(target));
get_timeout = true;
break;
}
alive_sleep(10);
xtensa_poll(target);
if (timeval_ms() >= timeout) {
- LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
- target->state);
+ LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state %s",
+ target_state_name(target));
return ERROR_TARGET_TIMEOUT;
}
}
xtensa_poll(target);
if (timeval_ms() >= timeout) {
LOG_TARGET_ERROR(target,
- "Timed out waiting for CPU to be reset, target state=%d",
- target->state);
+ "Timed out waiting for CPU to be reset, target state %s",
+ target_state_name(target));
get_timeout = true;
break;
}
uint8_t csr1, csr2;
#ifdef LOG_STM8
- LOG_DEBUG("target->state=%d", target->state);
+ LOG_DEBUG("target->state %s", target_state_name(target));
#endif
/* read dm_csrx control regs */
xtensa->smp_break = set;
if (target_was_examined(target))
res = xtensa_smpbreak_write(xtensa, xtensa->smp_break);
- LOG_TARGET_DEBUG(target, "set smpbreak=%" PRIx32 ", state=%i", set, target->state);
+ LOG_TARGET_DEBUG(target, "set smpbreak=%" PRIx32 ", state %s", set,
+ target_state_name(target));
return res;
}