]> www.infradead.org Git - users/dwmw2/linux.git/commitdiff
usb: xhci: Workaround for S3 issue on AMD SNPS 3.0 xHC
authorSandeep Singh <sandeep.singh@amd.com>
Wed, 28 Oct 2020 20:31:23 +0000 (22:31 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 5 Nov 2020 10:08:48 +0000 (11:08 +0100)
commit 2a632815683d2d34df52b701a36fe5ac6654e719 upstream.

On some platform of AMD, S3 fails with HCE and SRE errors. To fix this,
need to disable a bit which is enable in sparse controller.

Cc: stable@vger.kernel.org #v4.19+
Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Sandeep Singh <sandeep.singh@amd.com>
Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20201028203124.375344-3-mathias.nyman@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/usb/host/xhci-pci.c
drivers/usb/host/xhci.h

index 1a6a23e57201d6f4d524e2e1dd35e48b29c8d239..0c6b6f14b1696079e61cbfb7b95982102b54b343 100644 (file)
@@ -21,6 +21,8 @@
 #define SSIC_PORT_CFG2_OFFSET  0x30
 #define PROG_DONE              (1 << 30)
 #define SSIC_PORT_UNUSED       (1 << 31)
+#define SPARSE_DISABLE_BIT     17
+#define SPARSE_CNTL_ENABLE     0xC12C
 
 /* Device for a quirk */
 #define PCI_VENDOR_ID_FRESCO_LOGIC     0x1b73
@@ -141,6 +143,9 @@ static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
            (pdev->device == 0x15e0 || pdev->device == 0x15e1))
                xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
 
+       if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5)
+               xhci->quirks |= XHCI_DISABLE_SPARSE;
+
        if (pdev->vendor == PCI_VENDOR_ID_AMD)
                xhci->quirks |= XHCI_TRUST_TX_LENGTH;
 
@@ -441,6 +446,15 @@ static void xhci_pme_quirk(struct usb_hcd *hcd)
        readl(reg);
 }
 
+static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
+{
+       u32 reg;
+
+       reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
+       reg &= ~BIT(SPARSE_DISABLE_BIT);
+       writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
+}
+
 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 {
        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
@@ -460,6 +474,9 @@ static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
        if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
                xhci_ssic_port_unused_quirk(hcd, true);
 
+       if (xhci->quirks & XHCI_DISABLE_SPARSE)
+               xhci_sparse_control_quirk(hcd);
+
        ret = xhci_suspend(xhci, do_wakeup);
        if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
                xhci_ssic_port_unused_quirk(hcd, false);
index 39efbcf63c11d7f7cee63940e6c5155f931032a5..7a4195f8cd1ccaf31f722c5a7a8ea7add930c29c 100644 (file)
@@ -1872,6 +1872,7 @@ struct xhci_hcd {
 #define XHCI_ZERO_64B_REGS     BIT_ULL(32)
 #define XHCI_RESET_PLL_ON_DISCONNECT   BIT_ULL(34)
 #define XHCI_SNPS_BROKEN_SUSPEND    BIT_ULL(35)
+#define XHCI_DISABLE_SPARSE    BIT_ULL(38)
 
        unsigned int            num_active_eps;
        unsigned int            limit_active_eps;