ARM: imx: Get the silicon version from the IIM module

Instead of reading the silicon version from ROM, we should
read the SREV register from the IIM.

Freescale has dropped all support for MX51 REV1.0, only MX51
REV 2.0 and 3.0 are valid.

Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 98a25bada783fef44c1c5911dcc5cd7ca7ab8c9a..2202b88667b5350af6036cc4609fb22c750f108e 100644 (file)
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -125,7 +125,7 @@ static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
        if (clk->parent == parent)
                return 0;
 
-       if (mx27_revision() >= CHIP_REV_2_0) {
+       if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
                if (parent == &mpll_main1_clk) {
                        cscr |= CCM_CSCR_ARM_SRC;
                } else {
@@ -174,7 +174,7 @@ static int set_rate_cpu(struct clk *clk, unsigned long rate)
        div--;
 
        reg = __raw_readl(CCM_CSCR);
-       if (mx27_revision() >= CHIP_REV_2_0) {
+       if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
                reg &= ~(3 << 12);
                reg |= div << 12;
                reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
@@ -244,7 +244,7 @@ static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
 
        parent_rate = clk_get_rate(clk->parent);
 
-       if (mx27_revision() >= CHIP_REV_2_0)
+       if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                pdf += 4;  /* MX27 TO2+ */
        else
                pdf = (pdf < 2) ? 124UL : pdf;  /* MX21 & MX27 TO1 */
@@ -269,7 +269,7 @@ static unsigned long get_rate_nfc(struct clk *clk)
 
        parent_rate = clk_get_rate(clk->parent);
 
-       if (mx27_revision() >= CHIP_REV_2_0)
+       if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
        else
                nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
@@ -284,7 +284,7 @@ static unsigned long get_rate_vpu(struct clk *clk)
 
        parent_rate = clk_get_rate(clk->parent);
 
-       if (mx27_revision() >= CHIP_REV_2_0) {
+       if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
                vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
                vpu_pdf += 4;
        } else {
@@ -347,7 +347,7 @@ static unsigned long get_rate_mpll_main(struct clk *clk)
         * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
         * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
         */
-       if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
+       if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1)
                return 2UL * parent_rate / 3UL;
 
        return parent_rate;
@@ -365,7 +365,7 @@ static unsigned long get_rate_spll(struct clk *clk)
        /* On TO2 we have to write the value back. Otherwise we
         * read 0 from this register the next time.
         */
-       if (mx27_revision() >= CHIP_REV_2_0)
+       if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                __raw_writel(reg, CCM_SPCTL0);
 
        return mxc_decode_pll(reg, rate);
@@ -376,7 +376,7 @@ static unsigned long get_rate_cpu(struct clk *clk)
        u32 div;
        unsigned long rate;
 
-       if (mx27_revision() >= CHIP_REV_2_0)
+       if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
        else
                div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
@@ -389,7 +389,7 @@ static unsigned long get_rate_ahb(struct clk *clk)
 {
        unsigned long rate, bclk_pdf;
 
-       if (mx27_revision() >= CHIP_REV_2_0)
+       if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
        else
                bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
@@ -402,7 +402,7 @@ static unsigned long get_rate_ipg(struct clk *clk)
 {
        unsigned long rate, ipg_pdf;
 
-       if (mx27_revision() >= CHIP_REV_2_0)
+       if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
                return clk_get_rate(clk->parent);
        else
                ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
@@ -683,7 +683,7 @@ static void __init to2_adjust_clocks(void)
 {
        unsigned long cscr = __raw_readl(CCM_CSCR);
 
-       if (mx27_revision() >= CHIP_REV_2_0) {
+       if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
                if (cscr & CCM_CSCR_ARM_SRC)
                        cpu_clk.parent = &mpll_main1_clk;
 

diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index d8d3b2d84dc577df1cf432cea73c0be29fdaadc4..3b117be37bd2cd8cd6ce997ec294060045c44d11 100644 (file)
--- a/arch/arm/mach-imx/cpu-imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
@@ -42,7 +42,19 @@ static void query_silicon_parameter(void)
        val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
                                + SYS_CHIP_ID));
 
-       cpu_silicon_rev = (int)(val >> 28);
+       switch (val >> 28) {
+       case 0:
+               cpu_silicon_rev = IMX_CHIP_REVISION_1_0;
+               break;
+       case 1:
+               cpu_silicon_rev = IMX_CHIP_REVISION_2_0;
+               break;
+       case 2:
+               cpu_silicon_rev = IMX_CHIP_REVISION_2_1;
+               break;
+       default:
+               cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN;
+       }
        cpu_partnumber = (int)((val >> 12) & 0xFFFF);
 }
 

diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c
index 109e98f323e0568a299d46f1481ee3a31116476e..7cf6d29f376b5c8153d9344e2c2f984bab150959 100644 (file)
--- a/arch/arm/mach-mx3/clock-imx31.c
+++ b/arch/arm/mach-mx3/clock-imx31.c
@@ -615,7 +615,7 @@ int __init mx31_clocks_init(unsigned long fref)
 
        mx31_read_cpu_rev();
 
-       if (mx31_revision() >= MX31_CHIP_REV_2_0) {
+       if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
                reg = __raw_readl(MXC_CCM_PMCR1);
                /* No PLL restart on DVFS switch; enable auto EMI handshake */
                reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;

diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c
index d00a75457812eebc3f23eab759140a057ad6f8f8..d1d339576fdfe7900b4dd0f4723e536c9385da85 100644 (file)
--- a/arch/arm/mach-mx3/cpu.c
+++ b/arch/arm/mach-mx3/cpu.c
@@ -25,15 +25,15 @@ struct mx3_cpu_type {
 };
 
 static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
-       { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = MX3x_CHIP_REV_1_0 },
-       { .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = MX3x_CHIP_REV_1_1 },
-       { .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = MX3x_CHIP_REV_1_1 },
-       { .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
-       { .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = MX3x_CHIP_REV_1_1 },
-       { .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = MX3x_CHIP_REV_1_2 },
-       { .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = MX3x_CHIP_REV_1_2 },
-       { .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = MX3x_CHIP_REV_2_0 },
-       { .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = MX3x_CHIP_REV_2_0 },
+       { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0",  .rev = IMX_CHIP_REVISION_1_0  },
+       { .srev = 0x10, .name = "i.MX31",    .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1  },
+       { .srev = 0x11, .name = "i.MX31L",   .v = "1.1",  .rev = IMX_CHIP_REVISION_1_1  },
+       { .srev = 0x12, .name = "i.MX31",    .v = "1.15", .rev = IMX_CHIP_REVISION_1_1  },
+       { .srev = 0x13, .name = "i.MX31L",   .v = "1.15", .rev = IMX_CHIP_REVISION_1_1  },
+       { .srev = 0x14, .name = "i.MX31",    .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2  },
+       { .srev = 0x15, .name = "i.MX31L",   .v = "1.2",  .rev = IMX_CHIP_REVISION_1_2  },
+       { .srev = 0x28, .name = "i.MX31",    .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0  },
+       { .srev = 0x29, .name = "i.MX31L",   .v = "2.0",  .rev = IMX_CHIP_REVISION_2_0  },
 };
 
 void __init mx31_read_cpu_rev(void)
@@ -53,6 +53,8 @@ void __init mx31_read_cpu_rev(void)
                        return;
                }
 
+       mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
+
        printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
 }
 
@@ -62,22 +64,25 @@ EXPORT_SYMBOL(mx35_cpu_rev);
 void __init mx35_read_cpu_rev(void)
 {
        u32 rev;
-       char *srev = "unknown";
+       char *srev;
 
        rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
        switch (rev) {
        case 0x00:
-               mx35_cpu_rev = MX3x_CHIP_REV_1_0;
+               mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
                srev = "1.0";
                break;
        case 0x10:
-               mx35_cpu_rev = MX3x_CHIP_REV_2_0;
+               mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
                srev = "2.0";
                break;
        case 0x11:
-               mx35_cpu_rev = MX3x_CHIP_REV_2_1;
+               mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
                srev = "2.1";
                break;
+       default:
+               mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
+               srev = "unknown";
        }
 
        printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);

diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index ca4f9d58cfeb75801383685298e3a536ad88f963..344ee8ef1eef5b9c99d447c873ef7959da80c978 100644 (file)
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -780,6 +780,12 @@ static struct clk ahb_clk = {
        .round_rate = _clk_ahb_round_rate,
 };
 
+static struct clk iim_clk = {
+       .parent = &ipg_clk,
+       .enable_reg = MXC_CCM_CCGR0,
+       .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
+};
+
 /* Main IP interface clock for access to registers */
 static struct clk ipg_clk = {
        .parent = &ahb_clk,
@@ -1099,6 +1105,7 @@ static struct clk_lookup mx51_lookups[] = {
        _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
        _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
        _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
+       _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
 };
 
 static struct clk_lookup mx53_lookups[] = {
@@ -1107,6 +1114,7 @@ static struct clk_lookup mx53_lookups[] = {
        _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
        _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+       _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
 };
 
 static void clk_tree_init(void)
@@ -1147,6 +1155,10 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
        clk_enable(&cpu_clk);
        clk_enable(&main_bus_clk);
 
+       clk_enable(&iim_clk);
+       mx51_revision();
+       clk_disable(&iim_clk);
+
        /* set the usboh3_clk parent to pll2_sw_clk */
        clk_set_parent(&usboh3_clk, &pll2_sw_clk);
 
@@ -1182,6 +1194,10 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
        clk_enable(&cpu_clk);
        clk_enable(&main_bus_clk);
 
+       clk_enable(&iim_clk);
+       mx53_revision();
+       clk_disable(&iim_clk);
+
        /* System timer */
        mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
                MX53_INT_GPT);

diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index a00d2bc7246ae2c31c0f551aa4d5d4759824f4a0..d40671da4372a09a0e043a48bd1f6a8c7c44e60b 100644 (file)
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -20,37 +20,18 @@
 
 static int cpu_silicon_rev = -1;
 
-#define SI_REV 0x48
+#define IIM_SREV 0x24
 
-static void query_silicon_parameter(void)
+static int get_mx51_srev(void)
 {
-       void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
-       u32 rev;
+       void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
+       u32 rev = readl(iim_base + IIM_SREV) & 0xff;
 
-       if (!rom) {
-               cpu_silicon_rev = -EINVAL;
-               return;
-       }
-
-       rev = readl(rom + SI_REV);
-       switch (rev) {
-       case 0x1:
-               cpu_silicon_rev = MX51_CHIP_REV_1_0;
-               break;
-       case 0x2:
-               cpu_silicon_rev = MX51_CHIP_REV_1_1;
-               break;
-       case 0x10:
-               cpu_silicon_rev = MX51_CHIP_REV_2_0;
-               break;
-       case 0x20:
-               cpu_silicon_rev = MX51_CHIP_REV_3_0;
-               break;
-       default:
-               cpu_silicon_rev = 0;
-       }
-
-       iounmap(rom);
+       if (rev == 0x0)
+               return IMX_CHIP_REVISION_2_0;
+       else if (rev == 0x10)
+               return IMX_CHIP_REVISION_3_0;
+       return 0;
 }
 
 /*
@@ -64,7 +45,7 @@ int mx51_revision(void)
                return -EINVAL;
 
        if (cpu_silicon_rev == -1)
-               query_silicon_parameter();
+               cpu_silicon_rev = get_mx51_srev();
 
        return cpu_silicon_rev;
 }
@@ -82,7 +63,7 @@ static int __init mx51_neon_fixup(void)
        if (!cpu_is_mx51())
                return 0;
 
-       if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) {
+       if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
                elf_hwcap &= ~HWCAP_NEON;
                pr_info("Turning off NEON support, detected broken NEON implementation\n");
        }
@@ -92,6 +73,18 @@ static int __init mx51_neon_fixup(void)
 late_initcall(mx51_neon_fixup);
 #endif
 
+static int get_mx53_srev(void)
+{
+       void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
+       u32 rev = readl(iim_base + IIM_SREV) & 0xff;
+
+       if (rev == 0x0)
+               return IMX_CHIP_REVISION_1_0;
+       else if (rev == 0x10)
+               return IMX_CHIP_REVISION_2_0;
+       return 0;
+}
+
 /*
  * Returns:
  *     the silicon revision of the cpu
@@ -103,7 +96,7 @@ int mx53_revision(void)
                return -EINVAL;
 
        if (cpu_silicon_rev == -1)
-               query_silicon_parameter();
+               cpu_silicon_rev = get_mx53_srev();
 
        return cpu_silicon_rev;
 }

diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index cbaf282fb8182302d7ac2f881afa769adb4f8fbf..e57f96858f0dfb59e859ed08c860f644a3694150 100644 (file)
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -68,7 +68,7 @@ void __init mx51_init_irq(void)
        unsigned long tzic_addr;
        void __iomem *tzic_virt;
 
-       if (mx51_revision() < MX51_CHIP_REV_2_0)
+       if (mx51_revision() < IMX_CHIP_REVISION_2_0)
                tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
        else
                tzic_addr = MX51_TZIC_BASE_ADDR;

diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index eb09ec09dbe5edc22a6abd1aaf3df3f12e9c8684..cbc43ad5ef48e057c10c694f5ba644c9fa534235 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -244,10 +244,6 @@ static inline void mx27_setup_weimcs(size_t cs,
 #define MX27_DMA_REQ_SDHC3     36
 #define MX27_DMA_REQ_NFC       37
 
-/* silicon revisions specific to i.MX27 */
-#define CHIP_REV_1_0           0x00
-#define CHIP_REV_2_0           0x01
-
 #ifndef __ASSEMBLY__
 extern int mx27_revision(void);
 #endif

diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 092323144e2bc88d9a4830a036203b848ad9b687..79e7fc01bb59586b61cdb06b20a1d80eeb3e5221 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -203,20 +203,4 @@ static inline void mx31_setup_weimcs(size_t cs,
 
 #define MX31_PROD_SIGNATURE            0x1     /* For MX31 */
 
-/* silicon revisions specific to i.MX31 */
-#define MX31_CHIP_REV_1_0              0x10
-#define MX31_CHIP_REV_1_1              0x11
-#define MX31_CHIP_REV_1_2              0x12
-#define MX31_CHIP_REV_1_3              0x13
-#define MX31_CHIP_REV_2_0              0x20
-#define MX31_CHIP_REV_2_1              0x21
-#define MX31_CHIP_REV_2_2              0x22
-#define MX31_CHIP_REV_2_3              0x23
-#define MX31_CHIP_REV_3_0              0x30
-#define MX31_CHIP_REV_3_1              0x31
-#define MX31_CHIP_REV_3_2              0x32
-
-#define MX31_SYSTEM_REV_MIN            MX31_CHIP_REV_1_0
-#define MX31_SYSTEM_REV_NUM            3
-
 #endif /* ifndef __MACH_MX31_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 0fa3f6855349bda9e9a1c1d33e3b0a2236f4eb68..d13dbfeef08a2d4e2e744acebb3342a9ae14778a 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -186,7 +186,4 @@
 
 #define MX35_PROD_SIGNATURE            0x1     /* For MX31 */
 
-#define MX35_SYSTEM_REV_MIN            MX3x_CHIP_REV_1_0
-#define MX35_SYSTEM_REV_NUM            3
-
 #endif /* ifndef __MACH_MX35_H__ */

diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index 8c7f34e737d05b1dae2f7837bf2c45e1ba7308c6..388a407d72d667efddf1902c45eb9bd7cdb9ef90 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -184,22 +184,6 @@
 
 #define MX3x_PROD_SIGNATURE            0x1     /* For MX31 */
 
-/* silicon revisions specific to i.MX31 and i.MX35 */
-#define MX3x_CHIP_REV_1_0              0x10
-#define MX3x_CHIP_REV_1_1              0x11
-#define MX3x_CHIP_REV_1_2              0x12
-#define MX3x_CHIP_REV_1_3              0x13
-#define MX3x_CHIP_REV_2_0              0x20
-#define MX3x_CHIP_REV_2_1              0x21
-#define MX3x_CHIP_REV_2_2              0x22
-#define MX3x_CHIP_REV_2_3              0x23
-#define MX3x_CHIP_REV_3_0              0x30
-#define MX3x_CHIP_REV_3_1              0x31
-#define MX3x_CHIP_REV_3_2              0x32
-
-#define MX3x_SYSTEM_REV_MIN            MX3x_CHIP_REV_1_0
-#define MX3x_SYSTEM_REV_NUM            3
-
 /* Mandatory defines used globally */
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)

diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 636347c3fa889bf20a0ecd3ce091a5a0dca05f80..8fddfef9b4e82cbc06e840f5b3a48a601ba3aab3 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -345,19 +345,6 @@
 #define MX51_MXC_INT_EMI_NFC           101
 #define MX51_MXC_INT_GPU_IDLE          102
 
-/* silicon revisions specific to i.MX51 */
-#define MX51_CHIP_REV_1_0              0x10
-#define MX51_CHIP_REV_1_1              0x11
-#define MX51_CHIP_REV_1_2              0x12
-#define MX51_CHIP_REV_1_3              0x13
-#define MX51_CHIP_REV_2_0              0x20
-#define MX51_CHIP_REV_2_1              0x21
-#define MX51_CHIP_REV_2_2              0x22
-#define MX51_CHIP_REV_2_3              0x23
-#define MX51_CHIP_REV_3_0              0x30
-#define MX51_CHIP_REV_3_1              0x31
-#define MX51_CHIP_REV_3_2              0x32
-
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 extern int mx51_revision(void);
 #endif

diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 4c17515650b83a8805d8116f9830e218ce754046..4abbdd11d5c69fe90757a6fc67191d83506e55b4 100644 (file)
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -36,6 +36,20 @@
 #define MXC_CPU_MX53           53
 #define MXC_CPU_MXC91231       91231
 
+#define IMX_CHIP_REVISION_1_0          0x10
+#define IMX_CHIP_REVISION_1_1          0x11
+#define IMX_CHIP_REVISION_1_2          0x12
+#define IMX_CHIP_REVISION_1_3          0x13
+#define IMX_CHIP_REVISION_2_0          0x20
+#define IMX_CHIP_REVISION_2_1          0x21
+#define IMX_CHIP_REVISION_2_2          0x22
+#define IMX_CHIP_REVISION_2_3          0x23
+#define IMX_CHIP_REVISION_3_0          0x30
+#define IMX_CHIP_REVISION_3_1          0x31
+#define IMX_CHIP_REVISION_3_2          0x32
+#define IMX_CHIP_REVISION_3_3          0x33
+#define IMX_CHIP_REVISION_UNKNOWN      0xff
+
 #ifndef __ASSEMBLY__
 extern unsigned int __mxc_cpu_type;
 #endif