powerpc/perf: Fix to update cache events with l2l3 events in power10

Export l2l3 events (PM_L2_ST_MISS and PM_L2_ST) and LLC-prefetches
(PM_L3_PF_MISS_L3) via sysfs, and also add these to list of
cache_events.

Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1606409684-1589-7-git-send-email-atrajeev@linux.vnet.ibm.com

diff --git a/arch/powerpc/perf/power10-events-list.h b/arch/powerpc/perf/power10-events-list.h
index abd778f0dd5f7a51572b35242b53465c68e2ed40..e45dafe818ed417bf140d58c5debbfb611fa9b22 100644 (file)
--- a/arch/powerpc/perf/power10-events-list.h
+++ b/arch/powerpc/perf/power10-events-list.h
@@ -39,6 +39,12 @@ EVENT(PM_IC_PREF_REQ,                                0x040a0);
 EVENT(PM_DATA_FROM_L3,                         0x01340000001c040);
 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
 EVENT(PM_DATA_FROM_L3MISS,                     0x300fe);
+/* All successful D-side store dispatches for this thread */
+EVENT(PM_L2_ST,                                        0x010000046080);
+/* All successful D-side store dispatches for this thread that were L2 Miss */
+EVENT(PM_L2_ST_MISS,                           0x26880);
+/* Total HW L3 prefetches(Load+store) */
+EVENT(PM_L3_PF_MISS_L3,                                0x100000016080);
 /* Data PTEG reload */
 EVENT(PM_DTLB_MISS,                            0x300fc);
 /* ITLB Reloaded */

diff --git a/arch/powerpc/perf/power10-pmu.c b/arch/powerpc/perf/power10-pmu.c
index a02da69009971fe560506db672b11ec6b15d7422..79e0206ca4546d599304c45634f710655600dd50 100644 (file)
--- a/arch/powerpc/perf/power10-pmu.c
+++ b/arch/powerpc/perf/power10-pmu.c
@@ -127,6 +127,9 @@ CACHE_EVENT_ATTR(L1-icache-loads,           PM_INST_FROM_L1);
 CACHE_EVENT_ATTR(L1-icache-prefetches,         PM_IC_PREF_REQ);
 CACHE_EVENT_ATTR(LLC-load-misses,              PM_DATA_FROM_L3MISS);
 CACHE_EVENT_ATTR(LLC-loads,                    PM_DATA_FROM_L3);
+CACHE_EVENT_ATTR(LLC-prefetches,               PM_L3_PF_MISS_L3);
+CACHE_EVENT_ATTR(LLC-store-misses,             PM_L2_ST_MISS);
+CACHE_EVENT_ATTR(LLC-stores,                   PM_L2_ST);
 CACHE_EVENT_ATTR(branch-load-misses,           PM_BR_MPRED_CMPL);
 CACHE_EVENT_ATTR(branch-loads,                 PM_BR_CMPL);
 CACHE_EVENT_ATTR(dTLB-load-misses,             PM_DTLB_MISS);
@@ -175,6 +178,9 @@ static struct attribute *power10_events_attr[] = {
        CACHE_EVENT_PTR(PM_IC_PREF_REQ),
        CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
        CACHE_EVENT_PTR(PM_DATA_FROM_L3),
+       CACHE_EVENT_PTR(PM_L3_PF_MISS_L3),
+       CACHE_EVENT_PTR(PM_L2_ST_MISS),
+       CACHE_EVENT_PTR(PM_L2_ST),
        CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
        CACHE_EVENT_PTR(PM_BR_CMPL),
        CACHE_EVENT_PTR(PM_DTLB_MISS),
@@ -460,11 +466,11 @@ static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                        [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
                },
                [C(OP_WRITE)] = {
-                       [C(RESULT_ACCESS)] = -1,
-                       [C(RESULT_MISS)] = -1,
+                       [C(RESULT_ACCESS)] = PM_L2_ST,
+                       [C(RESULT_MISS)] = PM_L2_ST_MISS,
                },
                [C(OP_PREFETCH)] = {
-                       [C(RESULT_ACCESS)] = -1,
+                       [C(RESULT_ACCESS)] = PM_L3_PF_MISS_L3,
                        [C(RESULT_MISS)] = 0,
                },
        },