return plane_ctl;
 }
 
-static void skylake_update_primary_plane(struct intel_plane *plane,
-                                        const struct intel_crtc_state *crtc_state,
-                                        const struct intel_plane_state *plane_state)
-{
-       struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
-       const struct drm_framebuffer *fb = plane_state->base.fb;
-       enum plane_id plane_id = plane->id;
-       enum pipe pipe = plane->pipe;
-       u32 plane_ctl = plane_state->ctl;
-       unsigned int rotation = plane_state->base.rotation;
-       u32 stride = skl_plane_stride(fb, 0, rotation);
-       u32 aux_stride = skl_plane_stride(fb, 1, rotation);
-       u32 surf_addr = plane_state->main.offset;
-       int scaler_id = plane_state->scaler_id;
-       int src_x = plane_state->main.x;
-       int src_y = plane_state->main.y;
-       int src_w = drm_rect_width(&plane_state->base.src) >> 16;
-       int src_h = drm_rect_height(&plane_state->base.src) >> 16;
-       int dst_x = plane_state->base.dst.x1;
-       int dst_y = plane_state->base.dst.y1;
-       int dst_w = drm_rect_width(&plane_state->base.dst);
-       int dst_h = drm_rect_height(&plane_state->base.dst);
-       unsigned long irqflags;
-
-       /* Sizes are 0 based */
-       src_w--;
-       src_h--;
-       dst_w--;
-       dst_h--;
-
-       spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
-       if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
-               I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
-                             PLANE_COLOR_PIPE_GAMMA_ENABLE |
-                             PLANE_COLOR_PIPE_CSC_ENABLE |
-                             PLANE_COLOR_PLANE_GAMMA_DISABLE);
-       }
-
-       I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
-       I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
-       I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
-       I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
-       I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
-                     (plane_state->aux.offset - surf_addr) | aux_stride);
-       I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
-                     (plane_state->aux.y << 16) | plane_state->aux.x);
-
-       if (scaler_id >= 0) {
-               uint32_t ps_ctrl = 0;
-
-               WARN_ON(!dst_w || !dst_h);
-               ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
-                       crtc_state->scaler_state.scalers[scaler_id].mode;
-               I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
-               I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
-               I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
-               I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
-               I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
-       } else {
-               I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
-       }
-
-       I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
-                     intel_plane_ggtt_offset(plane_state) + surf_addr);
-
-       POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
-
-       spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-}
-
 static void skylake_disable_primary_plane(struct intel_plane *primary,
                                          struct intel_crtc *crtc)
 {
                num_formats = ARRAY_SIZE(skl_primary_formats);
                modifiers = skl_format_modifiers_ccs;
 
-               primary->update_plane = skylake_update_primary_plane;
+               primary->update_plane = skl_update_plane;
                primary->disable_plane = skylake_disable_primary_plane;
        } else if (INTEL_GEN(dev_priv) >= 9) {
                intel_primary_formats = skl_primary_formats;
                else
                        modifiers = skl_format_modifiers_noccs;
 
-               primary->update_plane = skylake_update_primary_plane;
+               primary->update_plane = skl_update_plane;
                primary->disable_plane = skylake_disable_primary_plane;
        } else if (INTEL_GEN(dev_priv) >= 4) {
                intel_primary_formats = i965_primary_formats;