drm/bridge: samsung-dsim: Fix porch calcalcuation rounding

The VFP, HBP, and HSA are divided between the available lanes if
there is more than one lane.  For certain timings and lane
configurations, the HFP may not be evenly divisible. If the HFP
is rounded down, it ends up being too small which can cause some
monitors to not sync properly. In these instances, adjust htotal
and hsync to round the HFP up, and recalculate the htotal.

This allows 720P-60 to operation on an i.MX8MP with a four-lane
configuration.

Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> # Kontron BL i.MX8MM with HDMI monitor
Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Robert Foss <rfoss@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20240601144103.198299-2-aford173@gmail.com

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index 8476650c477c250b60ee3769c14f06d290579f01..e7e53a9e42afbd21be9420afefbb0fe1a33a086c 100644 (file)
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -1606,6 +1606,27 @@ static int samsung_dsim_atomic_check(struct drm_bridge *bridge,
                adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
        }
 
+       /*
+        * When using video sync pulses, the HFP, HBP, and HSA are divided between
+        * the available lanes if there is more than one lane.  For certain
+        * timings and lane configurations, the HFP may not be evenly divisible.
+        * If the HFP is rounded down, it ends up being too small which can cause
+        * some monitors to not sync properly. In these instances, adjust htotal
+        * and hsync to round the HFP up, and recalculate the htotal. Through trial
+        * and error, it appears that the HBP and HSA do not appearto need the same
+        * correction that HFP does.
+        */
+       if (dsi->lanes > 1) {
+               int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay;
+               int remainder = hfp % dsi->lanes;
+
+               if (remainder) {
+                       adjusted_mode->hsync_start += remainder;
+                       adjusted_mode->hsync_end   += remainder;
+                       adjusted_mode->htotal      += remainder;
+               }
+       }
+
        return 0;
 }