phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified

It's possible that the Type-C plug orientation on the DIR line will be
implemented through hardware design. In that situation, there won't be
an external GPIO line available, but the driver still needs to address
this since the DT won't use the typec-dir-gpios property.

Add code to handle LN10 Type-C swap if typec-dir-gpios property is not
specified in DT.

Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230113150615.19375-2-sinthu.raja@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index ddce5ef7711c605541951e38698a18c79ec2f7e6..b5c1b82e99a6ee223de2042808785b32475d84d3 100644 (file)
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -376,6 +376,7 @@ struct wiz {
        struct gpio_desc        *gpio_typec_dir;
        int                     typec_dir_delay;
        u32 lane_phy_type[WIZ_MAX_LANES];
+       u32 master_lane_num[WIZ_MAX_LANES];
        struct clk              *input_clks[WIZ_MAX_INPUT_CLOCKS];
        struct clk              *output_clks[WIZ_MAX_OUTPUT_CLOCKS];
        struct clk_onecell_data clk_data;
@@ -1234,15 +1235,30 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
        struct wiz *wiz = dev_get_drvdata(dev);
        int ret;
 
-       /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
-       if (id == 0 && wiz->gpio_typec_dir) {
-               if (wiz->typec_dir_delay)
-                       msleep_interruptible(wiz->typec_dir_delay);
-
-               if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
-                       regmap_field_write(wiz->typec_ln10_swap, 1);
-               else
-                       regmap_field_write(wiz->typec_ln10_swap, 0);
+       if (id == 0) {
+               /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
+               if (wiz->gpio_typec_dir) {
+                       if (wiz->typec_dir_delay)
+                               msleep_interruptible(wiz->typec_dir_delay);
+
+                       if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
+                               regmap_field_write(wiz->typec_ln10_swap, 1);
+                       else
+                               regmap_field_write(wiz->typec_ln10_swap, 0);
+               } else {
+                       /* if no typec-dir gpio was specified and PHY type is
+                        * USB3 with master lane number is '0', set LN10 SWAP
+                        * bit to '1'
+                        */
+                       u32 num_lanes = wiz->num_lanes;
+                       int i;
+
+                       for (i = 0; i < num_lanes; i++) {
+                               if (wiz->lane_phy_type[i] == PHY_TYPE_USB3)
+                                       if (wiz->master_lane_num[i] == 0)
+                                               regmap_field_write(wiz->typec_ln10_swap, 1);
+                       }
+               }
        }
 
        if (id == 0) {
@@ -1386,8 +1402,10 @@ static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
                dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
                        reg, reg + num_lanes - 1, phy_type);
 
-               for (i = reg; i < reg + num_lanes; i++)
+               for (i = reg; i < reg + num_lanes; i++) {
+                       wiz->master_lane_num[i] = reg;
                        wiz->lane_phy_type[i] = phy_type;
+               }
        }
 
        return 0;