break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
                max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
                break;
                        *link_up = false;
        }
 
-       if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
-           IXGBE_LINKS_SPEED_10G_82599)
-               *speed = IXGBE_LINK_SPEED_10GB_FULL;
-       else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
-                IXGBE_LINKS_SPEED_1G_82599)
+       switch (links_reg & IXGBE_LINKS_SPEED_82599) {
+       case IXGBE_LINKS_SPEED_10G_82599:
+               if ((hw->mac.type >= ixgbe_mac_X550) &&
+                   (links_reg & IXGBE_LINKS_SPEED_NON_STD))
+                       *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
+               else
+                       *speed = IXGBE_LINK_SPEED_10GB_FULL;
+               break;
+       case IXGBE_LINKS_SPEED_1G_82599:
                *speed = IXGBE_LINK_SPEED_1GB_FULL;
-       else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
-                IXGBE_LINKS_SPEED_100_82599)
-               *speed = IXGBE_LINK_SPEED_100_FULL;
-       else
+               break;
+       case IXGBE_LINKS_SPEED_100_82599:
+               if ((hw->mac.type >= ixgbe_mac_X550) &&
+                   (links_reg & IXGBE_LINKS_SPEED_NON_STD))
+                       *speed = IXGBE_LINK_SPEED_5GB_FULL;
+               else
+                       *speed = IXGBE_LINK_SPEED_100_FULL;
+               break;
+       default:
                *speed = IXGBE_LINK_SPEED_UNKNOWN;
+       }
 
        return 0;
 }
 
                                                 bwgid, ptype);
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                return ixgbe_dcb_hw_config_82599(hw, pfc_en, refill, max,
                                                 bwgid, ptype, prio_tc);
        default:
                return ixgbe_dcb_config_pfc_82598(hw, pfc_en);
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                return ixgbe_dcb_config_pfc_82599(hw, pfc_en, prio_tc);
        default:
                break;
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max,
                                                  bwg_id, prio_type, prio_tc);
                ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
        switch (hw->mac.type) {
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                ixgbe_dcb_read_rtrup2tc_82599(hw, map);
                break;
        default:
 
        switch (adapter->hw.mac.type) {
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
                for (j = 0; j < netdev->addr_len; j++, i++)
                        perm_addr[i] = adapter->hw.mac.san_addr[j];
                break;
 
                        break;
                case ixgbe_mac_82599EB:
                case ixgbe_mac_X540:
+               case ixgbe_mac_X550:
+               case ixgbe_mac_X550EM_x:
                        regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
                        regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
                        break;
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
                regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
                for (i = 0; i < 8; i++)
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                toggle = 0x7FFFF30F;
                test = reg_test_82599;
                break;
        switch (hw->mac.type) {
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
                reg_ctl &= ~IXGBE_DMATXCTL_TE;
                IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
        switch (adapter->hw.mac.type) {
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
                reg_data |= IXGBE_DMATXCTL_TE;
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
        reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
        IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
 
-       /* X540 needs to set the MACC.FLU bit to force link up */
-       if (adapter->hw.mac.type == ixgbe_mac_X540) {
+       /* X540 and X550 needs to set the MACC.FLU bit to force link up */
+       switch (adapter->hw.mac.type) {
+       case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
                reg_data |= IXGBE_MACC_FLU;
                IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
-       } else {
+               break;
+       default:
                if (hw->mac.orig_autoc) {
                        reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
                        IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
        /* if we changed something we need to update flags */
        if (flags2 != adapter->flags2) {
                struct ixgbe_hw *hw = &adapter->hw;
-               u32 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
+               u32 mrqc;
+               unsigned int pf_pool = adapter->num_vfs;
+
+               if ((hw->mac.type >= ixgbe_mac_X550) &&
+                   (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
+                       mrqc = IXGBE_READ_REG(hw, IXGBE_PFVFMRQC(pf_pool));
+               else
+                       mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
 
                if ((flags2 & UDP_RSS_FLAGS) &&
                    !(adapter->flags2 & UDP_RSS_FLAGS))
                if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
                        mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
 
-               IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
+               if ((hw->mac.type >= ixgbe_mac_X550) &&
+                   (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
+                       IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), mrqc);
+               else
+                       IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
        }
 
        return 0;
        struct ixgbe_adapter *adapter = netdev_priv(dev);
 
        switch (adapter->hw.mac.type) {
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
        case ixgbe_mac_X540:
        case ixgbe_mac_82599EB:
                info->so_timestamping =
 
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                if (num_tcs > 4) {
                        /*
                         * TCs    : TC0/1 TC2/3 TC4-7
 
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                if (direction == -1) {
                        /* other causes */
                        msix_vector |= IXGBE_IVAR_ALLOC_VAL;
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                mask = (qmask & 0xFFFFFFFF);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
                mask = (qmask >> 32);
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                ixgbe_set_ivar(adapter, -1, 1, v_idx);
                break;
        default:
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                /*
                 * set the WDIS bit to not clear the timer bits and cause an
                 * immediate assertion of the interrupt
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                mask = (qmask & 0xFFFFFFFF);
                if (mask)
                        IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                mask = (qmask & 0xFFFFFFFF);
                if (mask)
                        IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
                        mask |= IXGBE_EIMS_GPI_SDP0;
                        break;
                case ixgbe_mac_X540:
+               case ixgbe_mac_X550:
+               case ixgbe_mac_X550EM_x:
                        mask |= IXGBE_EIMS_TS;
                        break;
                default:
        case ixgbe_mac_82599EB:
                mask |= IXGBE_EIMS_GPI_SDP1;
                mask |= IXGBE_EIMS_GPI_SDP2;
+               /* fall through */
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                mask |= IXGBE_EIMS_ECC;
                mask |= IXGBE_EIMS_MAILBOX;
                break;
                break;
        }
 
-       if (adapter->hw.mac.type == ixgbe_mac_X540)
-               mask |= IXGBE_EIMS_TIMESYNC;
-
        if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
            !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
                mask |= IXGBE_EIMS_FLOW_DIR;
        switch (hw->mac.type) {
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                if (eicr & IXGBE_EICR_ECC) {
                        e_info(link, "Received ECC Err, initiating reset\n");
                        adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
                ixgbe_check_sfp_event(adapter, eicr);
                /* Fall through */
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                if (eicr & IXGBE_EICR_ECC) {
                        e_info(link, "Received ECC Err, initiating reset\n");
                        adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
        u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 
        switch (hw->mac.type) {
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
        case ixgbe_mac_82598EB:
                /*
                 * For VMDq support of different descriptor types or
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                for (i = 0; i < adapter->num_rx_queues; i++) {
                        struct ixgbe_ring *ring = adapter->rx_ring[i];
 
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                for (i = 0; i < adapter->num_rx_queues; i++) {
                        struct ixgbe_ring *ring = adapter->rx_ring[i];
 
        /* Calculate delay value for device */
        switch (hw->mac.type) {
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                dv_id = IXGBE_DV_X540(link, tc);
                break;
        default:
        /* Calculate delay value for device */
        switch (hw->mac.type) {
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                dv_id = IXGBE_LOW_DV_X540(tc);
                break;
        default:
                        break;
                case ixgbe_mac_82599EB:
                case ixgbe_mac_X540:
+               case ixgbe_mac_X550:
+               case ixgbe_mac_X550EM_x:
                default:
                        IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
                        IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
                IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
        }
 
-       /* Disable the Tx DMA engine on 82599 and X540 */
+       /* Disable the Tx DMA engine on 82599 and later MAC */
        switch (hw->mac.type) {
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
                                (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
                                 ~IXGBE_DMATXCTL_TE));
                if (fwsm & IXGBE_FWSM_TS_ENABLED)
                        adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
                break;
+       case ixgbe_mac_X550EM_x:
+       case ixgbe_mac_X550:
+#ifdef CONFIG_IXGBE_DCA
+               adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
+#endif
+               break;
        default:
                break;
        }
 #ifdef CONFIG_IXGBE_DCB
        switch (hw->mac.type) {
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
                adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
                break;
                break;
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                pci_wake_from_d3(pdev, !!wufc);
                break;
        default:
                        break;
                case ixgbe_mac_82599EB:
                case ixgbe_mac_X540:
+               case ixgbe_mac_X550:
+               case ixgbe_mac_X550EM_x:
                        hwstats->pxonrxc[i] +=
                                IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
                        break;
                hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
                hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
                if ((hw->mac.type == ixgbe_mac_82599EB) ||
-                   (hw->mac.type == ixgbe_mac_X540)) {
+                   (hw->mac.type == ixgbe_mac_X540) ||
+                   (hw->mac.type == ixgbe_mac_X550) ||
+                   (hw->mac.type == ixgbe_mac_X550EM_x)) {
                        hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
                        IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
                        hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
                hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
                break;
        case ixgbe_mac_X540:
-               /* OS2BMC stats are X540 only*/
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
+               /* OS2BMC stats are X540 and later */
                hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
                hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
                hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
        }
                break;
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
        case ixgbe_mac_82599EB: {
                u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
                u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
        if (!adapter->num_vfs)
                return false;
 
+       /* resetting the PF is only needed for MAC before X550 */
+       if (hw->mac.type >= ixgbe_mac_X550)
+               return false;
+
        for (i = 0; i < adapter->num_vfs; i++) {
                for (j = 0; j < q_per_pool; j++) {
                        u32 h, t;
                ciaa = (vf << 16) | 0x80000000;
                /* 32 bit read so align, we really want status at offset 6 */
                ciaa |= PCI_COMMAND;
-               IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
-               ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
+               IXGBE_WRITE_REG(hw, IXGBE_CIAA_BY_MAC(hw), ciaa);
+               ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_BY_MAC(hw));
                ciaa &= 0x7FFFFFFF;
                /* disable debug mode asap after reading data */
-               IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
+               IXGBE_WRITE_REG(hw, IXGBE_CIAA_BY_MAC(hw), ciaa);
                /* Get the upper 16 bits which will be the PCI status reg */
                ciad >>= 16;
                if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
                        /* Issue VFLR */
                        ciaa = (vf << 16) | 0x80000000;
                        ciaa |= 0xA8;
-                       IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
+                       IXGBE_WRITE_REG(hw, IXGBE_CIAA_BY_MAC(hw), ciaa);
                        ciad = 0x00008000;  /* VFLR */
-                       IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
+                       IXGBE_WRITE_REG(hw, IXGBE_CIAD_BY_MAC(hw), ciad);
                        ciaa &= 0x7FFFFFFF;
-                       IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
+                       IXGBE_WRITE_REG(hw, IXGBE_CIAA_BY_MAC(hw), ciaa);
                }
        }
 }
        switch (adapter->hw.mac.type) {
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
                break;
        default:
        switch (adapter->hw.mac.type) {
        case ixgbe_mac_82599EB:
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                netdev->features |= NETIF_F_SCTP_CSUM;
                netdev->hw_features |= NETIF_F_SCTP_CSUM |
                                       NETIF_F_NTUPLE;
                case ixgbe_mac_X540:
                        device_id = IXGBE_X540_VF_DEVICE_ID;
                        break;
+               case ixgbe_mac_X550:
+                       device_id = IXGBE_DEV_ID_X550_VF;
+                       break;
+               case ixgbe_mac_X550EM_x:
+                       device_id = IXGBE_DEV_ID_X550EM_X_VF;
+                       break;
                default:
                        device_id = 0;
                        break;
 
                vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset));
                break;
        case ixgbe_mac_X540:
+       case ixgbe_mac_X550:
+       case ixgbe_mac_X550EM_x:
                vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset));
                break;
        default:
        struct ixgbe_mbx_info *mbx = &hw->mbx;
 
        if (hw->mac.type != ixgbe_mac_82599EB &&
+           hw->mac.type != ixgbe_mac_X550 &&
+           hw->mac.type != ixgbe_mac_X550EM_x &&
            hw->mac.type != ixgbe_mac_X540)
                return;
 
 
 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
-static bool ixgbe_get_i2c_data(u32 *i2cctl);
+static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
                        *speed |= IXGBE_LINK_SPEED_100_FULL;
        }
 
+       /* Internal PHY does not support 100 Mbps */
+       if (hw->mac.type == ixgbe_mac_X550EM_x)
+               *speed &= ~IXGBE_LINK_SPEED_100_FULL;
+
        return status;
 }
 
  *     @hw: pointer to hardware structure
  *
  *     Restart autonegotiation and PHY and waits for completion.
+ *      This function always returns success, this is nessary since
+ *     it is called via a function pointer that could call other
+ *     functions that could return an error.
  **/
 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 {
-       s32 status;
        u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
        bool autoneg = false;
        ixgbe_link_speed speed;
        hw->phy.ops.write_reg(hw, MDIO_CTRL1,
                              MDIO_MMD_AN, autoneg_reg);
 
-       return status;
+       return 0;
 }
 
 /**
  **/
 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
 {
-       u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+       u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
 
        /* Start condition must begin with data and clock high */
        ixgbe_set_i2c_data(hw, &i2cctl, 1);
  **/
 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
 {
-       u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+       u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
 
        /* Stop condition must begin with data low and clock high */
        ixgbe_set_i2c_data(hw, &i2cctl, 0);
        }
 
        /* Release SDA line (set high) */
-       i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
-       i2cctl |= IXGBE_I2C_DATA_OUT;
-       IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
+       i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
+       i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
+       IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
        IXGBE_WRITE_FLUSH(hw);
 
        return status;
 {
        s32 status = 0;
        u32 i = 0;
-       u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+       u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
        u32 timeout = 10;
        bool ack = true;
 
        /* Poll for ACK.  Note that ACK in I2C spec is
         * transition from 1 to 0 */
        for (i = 0; i < timeout; i++) {
-               i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
-               ack = ixgbe_get_i2c_data(&i2cctl);
+               i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
+               ack = ixgbe_get_i2c_data(hw, &i2cctl);
 
                udelay(1);
                if (ack == 0)
  **/
 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
 {
-       u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+       u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
 
        ixgbe_raise_i2c_clk(hw, &i2cctl);
 
        /* Minimum high period of clock is 4us */
        udelay(IXGBE_I2C_T_HIGH);
 
-       i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
-       *data = ixgbe_get_i2c_data(&i2cctl);
+       i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
+       *data = ixgbe_get_i2c_data(hw, &i2cctl);
 
        ixgbe_lower_i2c_clk(hw, &i2cctl);
 
 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
 {
        s32 status;
-       u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+       u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
 
        status = ixgbe_set_i2c_data(hw, &i2cctl, data);
        if (status == 0) {
        u32 i2cctl_r = 0;
 
        for (i = 0; i < timeout; i++) {
-               *i2cctl |= IXGBE_I2C_CLK_OUT;
-               IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+               *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
+               IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
                IXGBE_WRITE_FLUSH(hw);
                /* SCL rise time (1000ns) */
                udelay(IXGBE_I2C_T_RISE);
 
-               i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
-               if (i2cctl_r & IXGBE_I2C_CLK_IN)
+               i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
+               if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
                        break;
        }
 }
 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
 {
 
-       *i2cctl &= ~IXGBE_I2C_CLK_OUT;
+       *i2cctl &= ~IXGBE_I2C_CLK_OUT_BY_MAC(hw);
 
-       IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+       IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
        IXGBE_WRITE_FLUSH(hw);
 
        /* SCL fall time (300ns) */
 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
 {
        if (data)
-               *i2cctl |= IXGBE_I2C_DATA_OUT;
+               *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
        else
-               *i2cctl &= ~IXGBE_I2C_DATA_OUT;
+               *i2cctl &= ~IXGBE_I2C_DATA_OUT_BY_MAC(hw);
 
-       IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
+       IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
        IXGBE_WRITE_FLUSH(hw);
 
        /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
        udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
 
        /* Verify data was set correctly */
-       *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
-       if (data != ixgbe_get_i2c_data(i2cctl)) {
+       *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
+       if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
                hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
                return IXGBE_ERR_I2C;
        }
  *
  *  Returns the I2C data bit value
  **/
-static bool ixgbe_get_i2c_data(u32 *i2cctl)
+static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
 {
-       if (*i2cctl & IXGBE_I2C_DATA_IN)
+       if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
                return true;
        return false;
 }
  **/
 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
 {
-       u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
+       u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
        u32 i;
 
        ixgbe_i2c_start(hw);
 
        if (adapter->vfinfo[vf].spoofchk_enabled)
                hw->mac.ops.set_vlan_anti_spoofing(hw, true, vf);
        adapter->vfinfo[vf].vlan_count++;
+
+       /* enable hide vlan on X550 */
+       if (hw->mac.type >= ixgbe_mac_X550)
+               ixgbe_write_qde(adapter, vf, IXGBE_QDE_ENABLE |
+                               IXGBE_QDE_HIDE_VLAN);
+
        adapter->vfinfo[vf].pf_vlan = vlan;
        adapter->vfinfo[vf].pf_qos = qos;
        dev_info(&adapter->pdev->dev,
 
 /* VF Device IDs */
 #define IXGBE_DEV_ID_82599_VF           0x10ED
 #define IXGBE_DEV_ID_X540_VF            0x1515
+#define IXGBE_DEV_ID_X550_VF           0x1565
+#define IXGBE_DEV_ID_X550EM_X_VF       0x15A8
 
 /* General Registers */
 #define IXGBE_CTRL      0x00000
 #define IXGBE_CTRL_EXT  0x00018
 #define IXGBE_ESDP      0x00020
 #define IXGBE_EODSDP    0x00028
-#define IXGBE_I2CCTL    0x00028
+#define IXGBE_I2CCTL_BY_MAC(_hw)((((_hw)->mac.type >= ixgbe_mac_X550) ? \
+                                       0x15F5C : 0x00028))
 #define IXGBE_LEDCTL    0x00200
 #define IXGBE_FRTIMER   0x00048
 #define IXGBE_TCPTIMER  0x0004C
 #define IXGBE_VPDDIAG1  0x10208
 
 /* I2CCTL Bit Masks */
-#define IXGBE_I2C_CLK_IN    0x00000001
-#define IXGBE_I2C_CLK_OUT   0x00000002
-#define IXGBE_I2C_DATA_IN   0x00000004
-#define IXGBE_I2C_DATA_OUT  0x00000008
+#define IXGBE_I2C_CLK_IN_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
+                                       0x00004000 : 0x00000001)
+#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
+                                       0x00000200 : 0x00000002)
+#define IXGBE_I2C_DATA_IN_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
+                                       0x00001000 : 0x00000004)
+#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw)(((_hw)->mac.type) >= ixgbe_mac_X550 ? \
+                                       0x00000400 : 0x00000008)
 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT     500
 
 #define IXGBE_I2C_THERMAL_SENSOR_ADDR  0xF8
 #define IXGBE_RETA(_i)  (0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
 
+/* Registers for setting up RSS on X550 with SRIOV
+ * _p - pool number (0..63)
+ * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA)
+ */
+#define IXGBE_PFVFMRQC(_p)     (0x03400 + ((_p) * 4))
+#define IXGBE_PFVFRSSRK(_i, _p)        (0x018000 + ((_i) * 4) + ((_p) * 0x40))
+#define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40))
+
 /* Flow Director registers */
 #define IXGBE_FDIRCTRL  0x0EE00
 #define IXGBE_FDIRHKEY  0x0EE68
 #define IXGBE_PBACLR_82599      0x11068
 #define IXGBE_CIAA_82599        0x11088
 #define IXGBE_CIAD_82599        0x1108C
+#define IXGBE_CIAA_X550         0x11508
+#define IXGBE_CIAD_X550         0x11510
+#define IXGBE_CIAA_BY_MAC(_hw)  ((((_hw)->mac.type >= ixgbe_mac_X550) ? \
+                               IXGBE_CIAA_X550 : IXGBE_CIAA_82599))
+#define IXGBE_CIAD_BY_MAC(_hw)  ((((_hw)->mac.type >= ixgbe_mac_X550) ? \
+                               IXGBE_CIAD_X550 : IXGBE_CIAD_82599))
 #define IXGBE_PICAUSE           0x110B0
 #define IXGBE_PIENA             0x110B8
 #define IXGBE_CDQ_MBR_82599     0x110B4
 #define IXGBE_LINKS_TL_FAULT    0x00001000
 #define IXGBE_LINKS_SIGNAL      0x00000F00
 
+#define IXGBE_LINKS_SPEED_NON_STD   0x08000000
 #define IXGBE_LINKS_SPEED_82599     0x30000000
 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000
 #define IXGBE_LINKS_SPEED_1G_82599  0x20000000
 
 /* Queue Drop Enable */
 #define IXGBE_QDE_ENABLE       0x00000001
+#define IXGBE_QDE_HIDE_VLAN    0x00000002
 #define IXGBE_QDE_IDX_MASK     0x00007F00
 #define IXGBE_QDE_IDX_SHIFT    8
 #define IXGBE_QDE_WRITE                0x00010000
 typedef u32 ixgbe_autoneg_advertised;
 /* Link speed */
 typedef u32 ixgbe_link_speed;
-#define IXGBE_LINK_SPEED_UNKNOWN   0
-#define IXGBE_LINK_SPEED_100_FULL  0x0008
-#define IXGBE_LINK_SPEED_1GB_FULL  0x0020
-#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
+#define IXGBE_LINK_SPEED_UNKNOWN       0
+#define IXGBE_LINK_SPEED_100_FULL      0x0008
+#define IXGBE_LINK_SPEED_1GB_FULL      0x0020
+#define IXGBE_LINK_SPEED_2_5GB_FULL    0x0400
+#define IXGBE_LINK_SPEED_5GB_FULL      0x0800
+#define IXGBE_LINK_SPEED_10GB_FULL     0x0080
 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
                                        IXGBE_LINK_SPEED_10GB_FULL)
 #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
        ixgbe_mac_82598EB,
        ixgbe_mac_82599EB,
        ixgbe_mac_X540,
+       ixgbe_mac_X550,
+       ixgbe_mac_X550EM_x,
        ixgbe_num_macs
 };