arm64/sysreg: Convert CTR_EL0 to automatic generation

Convert CTR_EL0 to automatic register generation as per DDI0487H.a, no
functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-18-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 0b547f181fb07e90d5ce26082e2f76f2ff8f37f7..234f9a3844de60ba7c8013b3aef2570a44642358 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -461,7 +461,6 @@
 #define SMIDR_EL1_SMPS_SHIFT   15
 #define SMIDR_EL1_AFFINITY_SHIFT       0
 
-#define SYS_CTR_EL0                    sys_reg(3, 3, 0, 0, 1)
 #define SYS_DCZID_EL0                  sys_reg(3, 3, 0, 0, 7)
 
 #define SYS_RNDR_EL0                   sys_reg(3, 3, 2, 4, 0)
@@ -1082,21 +1081,6 @@
 #define MVFR2_FPMISC_SHIFT             4
 #define MVFR2_SIMDMISC_SHIFT           0
 
-#define CTR_EL0_L1Ip_VPIPT             0
-#define CTR_EL0_L1Ip_VIPT              2
-#define CTR_EL0_L1Ip_PIPT              3
-
-#define CTR_EL0_L1Ip_SHIFT             14
-#define CTR_EL0_L1Ip_MASK              3
-#define CTR_EL0_DminLine_SHIFT         16
-#define CTR_EL0_IminLine_SHIFT         0
-#define CTR_EL0_IminLine_MASK          0xf
-#define CTR_EL0_ERG_SHIFT              20
-#define CTR_EL0_CWG_SHIFT              24
-#define CTR_EL0_CWG_MASK               15
-#define CTR_EL0_IDC_SHIFT              28
-#define CTR_EL0_DIC_SHIFT              29
-
 #define DCZID_EL0_DZP_SHIFT            4
 #define DCZID_EL0_BS_SHIFT             0
 

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index ff5e552f7420973f51aa08a11bda711fd35a9f29..a9f4c157c4be917c6c5dc4b1022c33fd3c0e706a 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -273,6 +273,27 @@ Field      3:1     Level
 Field  0       InD
 EndSysreg
 
+Sysreg CTR_EL0 3       3       0       0       1
+Res0   63:38
+Field  37:32   TminLine
+Res1   31
+Res0   30
+Field  29      DIC
+Field  28      IDC
+Field  27:24   CWG
+Field  23:20   ERG
+Field  19:16   DminLine
+Enum   15:14   L1Ip
+       0b00    VPIPT
+       # This is named as AIVIVT in the ARM but documented as reserved
+       0b01    RESERVED
+       0b10    VIPT
+       0b11    PIPT
+EndEnum
+Res0   13:4
+Field  3:0     IminLine
+EndSysreg
+
 Sysreg SVCR    3       3       4       2       2
 Res0   63:2
 Field  1       ZA