arm64/sysreg: Standardise naming for WFxT defines

The defines for WFxT refer to the feature as WFXT and use SUPPORTED rather
than IMP. In preparation for automatic generation of defines update these
to be more standard. No functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-12-broonie@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 34bf421c52dfab6838081721e570da56be91aeef..1b1ea5bd01c0396215677829f7c352976809d86b 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -742,7 +742,7 @@
 #define ID_AA64ISAR2_APA3_SHIFT                12
 #define ID_AA64ISAR2_GPA3_SHIFT                8
 #define ID_AA64ISAR2_RPRES_SHIFT       4
-#define ID_AA64ISAR2_WFXT_SHIFT                0
+#define ID_AA64ISAR2_WFxT_SHIFT                0
 
 #define ID_AA64ISAR2_RPRES_8BIT                0x0
 #define ID_AA64ISAR2_RPRES_12BIT       0x1
@@ -751,8 +751,8 @@
  * reserved, but has not yet been removed from the ARM ARM
  * as of ARM DDI 0487G.b.
  */
-#define ID_AA64ISAR2_WFXT_NI           0x0
-#define ID_AA64ISAR2_WFXT_SUPPORTED    0x2
+#define ID_AA64ISAR2_WFxT_NI           0x0
+#define ID_AA64ISAR2_WFxT_IMP          0x2
 
 #define ID_AA64ISAR2_APA3_NI                   0x0
 #define ID_AA64ISAR2_APA3_PAuth                        0x1

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 0f9c9d8b21a2b8e23e9862aff28a4a5affc61d01..83f8e9d360cec997bfb23173778376e944745ac2 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -237,7 +237,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
        ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
                       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_GPA3_SHIFT, 4, 0),
        ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_RPRES_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFXT_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_WFxT_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
@@ -2516,10 +2516,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .type = ARM64_CPUCAP_SYSTEM_FEATURE,
                .sys_reg = SYS_ID_AA64ISAR2_EL1,
                .sign = FTR_UNSIGNED,
-               .field_pos = ID_AA64ISAR2_WFXT_SHIFT,
+               .field_pos = ID_AA64ISAR2_WFxT_SHIFT,
                .field_width = 4,
                .matches = has_cpuid_feature,
-               .min_field_value = ID_AA64ISAR2_WFXT_SUPPORTED,
+               .min_field_value = ID_AA64ISAR2_WFxT_IMP,
        },
        {},
 };
@@ -2654,7 +2654,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
        HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
        HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
        HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
-       HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFXT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFXT_SUPPORTED, CAP_HWCAP, KERNEL_HWCAP_WFXT),
+       HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
 #ifdef CONFIG_ARM64_SME
        HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SME_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_SME, CAP_HWCAP, KERNEL_HWCAP_SME),
        HWCAP_CAP(SYS_ID_AA64SMFR0_EL1, ID_AA64SMFR0_FA64_SHIFT, 1, FTR_UNSIGNED, ID_AA64SMFR0_FA64, CAP_HWCAP, KERNEL_HWCAP_SME_FA64),

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c06c0477fab526deb0f89ee2148d605446f34691..f12c6d4576779765442994842d36dad24472247a 100644 (file)
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1146,7 +1146,7 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
                        val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_APA3) |
                                 ARM64_FEATURE_MASK(ID_AA64ISAR2_GPA3));
                if (!cpus_have_final_cap(ARM64_HAS_WFXT))
-                       val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_WFXT);
+                       val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_WFxT);
                break;
        case SYS_ID_AA64DFR0_EL1:
                /* Limit debug to ARMv8.0 */