static u32 fmt_to_reg(struct mmp_overlay *overlay, int pix_fmt)
 {
-       u32 link_config = path_to_path_plat(overlay->path)->link_config;
-       u32 rbswap, uvswap = 0, yuvswap = 0,
+       u32 rbswap = 0, uvswap = 0, yuvswap = 0,
                csc_en = 0, val = 0,
                vid = overlay_is_vid(overlay);
 
        case PIXFMT_RGB888PACK:
        case PIXFMT_RGB888UNPACK:
        case PIXFMT_RGBA888:
-               rbswap = !(link_config & 0x1);
+               rbswap = 1;
                break;
        case PIXFMT_VYUY:
        case PIXFMT_YVU422P:
        case PIXFMT_YVU420P:
-               rbswap = link_config & 0x1;
                uvswap = 1;
                break;
        case PIXFMT_YUYV:
-               rbswap = link_config & 0x1;
                yuvswap = 1;
                break;
        default:
-               rbswap = link_config & 0x1;
                break;
        }
 
        switch (pix_fmt) {
        case PIXFMT_RGB565:
        case PIXFMT_BGR565:
-               val = 0;
                break;
        case PIXFMT_RGB1555:
        case PIXFMT_BGR1555:
 {
        struct lcd_regs *regs = path_regs(path);
        u32 total_x, total_y, vsync_ctrl, tmp, sclk_src, sclk_div,
-               link_config = path_to_path_plat(path)->link_config;
+               link_config = path_to_path_plat(path)->link_config,
+               dsi_rbswap = path_to_path_plat(path)->link_config;
 
        /* FIXME: assert videomode supported */
        memcpy(&path->mode, mode, sizeof(struct mmp_mode));
        tmp |= CFG_DUMB_ENA(1);
        writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));
 
+       /* interface rb_swap setting */
+       tmp = readl_relaxed(ctrl_regs(path) + intf_rbswap_ctrl(path->id)) &
+               (~(CFG_INTFRBSWAP_MASK));
+       tmp |= dsi_rbswap & CFG_INTFRBSWAP_MASK;
+       writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));
+
        writel_relaxed((mode->yres << 16) | mode->xres, ®s->screen_active);
        writel_relaxed((mode->left_margin << 16) | mode->right_margin,
                ®s->screen_h_porch);
        path_plat->path = path;
        path_plat->path_config = config->path_config;
        path_plat->link_config = config->link_config;
+       path_plat->dsi_rbswap = config->dsi_rbswap;
        path_set_default(path);
 
        kfree(path_info);
 
 
 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
        ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
+#define intf_rbswap_ctrl(id)   ((id) ? (((id) & 1) ? LCD_TVIF_CTRL : \
+                               PN2_IOPAD_CONTROL) : LCD_TOP_CTRL)
 
 /* dither configure */
 #ifdef CONFIG_CPU_PXA988
 #define LCD_SPU_DUMB_CTRL                      0x01B8
 #define         CFG_DUMBMODE(mode)                     ((mode)<<28)
 #define         CFG_DUMBMODE_MASK                      0xF0000000
+#define         CFG_INTFRBSWAP(mode)                   ((mode)<<24)
+#define         CFG_INTFRBSWAP_MASK                    0x0F000000
 #define         CFG_LCDGPIO_O(data)                    ((data)<<20)
 #define         CFG_LCDGPIO_O_MASK                     0x0FF00000
 #define         CFG_LCDGPIO_ENA(gpio)                  ((gpio)<<12)
        struct mmp_path *path;
        u32 path_config;
        u32 link_config;
+       u32 dsi_rbswap;
 };
 
 /* mmp ctrl describes mmp controller related info */