drm/radeon: add UVD tiling addr config v2

v2: set UVD tiling config for rv730

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index a6e71864ee8318e5a7e26238758d8ad5c37b0783..c6d80175d18bcc31bf788fdf42b9275dc30b47d2 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2269,6 +2269,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
        WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
        WREG32(HDP_ADDR_CONFIG, gb_addr_config);
        WREG32(DMA_TILING_CONFIG, gb_addr_config);
+       WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
+       WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
+       WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
 
        if ((rdev->config.evergreen.max_backends == 1) &&
            (rdev->flags & RADEON_IS_IGP)) {

diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 43e7d3f53c554eaa301b9588a75f3d006e2f9320..eabf92af84e504bd84d540ba454367445ecdf5a9 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1033,6 +1033,9 @@
 /*
  * UVD
  */
+#define UVD_UDEC_ADDR_CONFIG                           0xef4c
+#define UVD_UDEC_DB_ADDR_CONFIG                                0xef50
+#define UVD_UDEC_DBW_ADDR_CONFIG                       0xef54
 #define UVD_RBC_RB_RPTR                                        0xf690
 #define UVD_RBC_RB_WPTR                                        0xf694
 

diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 35d7caa60c4869c195f0af6876a628f68ce728be..a23503e16083c982dd737b9602e8ed3d153e03c3 100644 (file)
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -626,6 +626,9 @@ static void cayman_gpu_init(struct radeon_device *rdev)
        WREG32(HDP_ADDR_CONFIG, gb_addr_config);
        WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
        WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
+       WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
+       WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
+       WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
 
        if ((rdev->config.cayman.max_backends_per_se == 1) &&
            (rdev->flags & RADEON_IS_IGP)) {

diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index f2555bc44ada335d80ab844d1392dd16a555a276..71a1709de1546f63a5c83efd594fc2862e2c40d5 100644 (file)
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -495,6 +495,9 @@
 #define UVD_SEMA_ADDR_LOW                              0xEF00
 #define UVD_SEMA_ADDR_HIGH                             0xEF04
 #define UVD_SEMA_CMD                                   0xEF08
+#define UVD_UDEC_ADDR_CONFIG                           0xEF4C
+#define UVD_UDEC_DB_ADDR_CONFIG                                0xEF50
+#define UVD_UDEC_DBW_ADDR_CONFIG                       0xEF54
 #define UVD_RBC_RB_RPTR                                        0xF690
 #define UVD_RBC_RB_WPTR                                        0xF694
 

diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index c8a5e67d7cdacd2579622f3d049360b5bad96c74..7bce3b8ba50bea03e665f7b41bc1cfcf8c5de45d 100644 (file)
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -866,6 +866,11 @@ static void rv770_gpu_init(struct radeon_device *rdev)
        WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
        WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
        WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
+       if (rdev->family == CHIP_RV730) {
+               WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
+               WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
+               WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
+       }
 
        WREG32(CGTS_SYS_TCC_DISABLE, 0);
        WREG32(CGTS_TCC_DISABLE, 0);

diff --git a/drivers/gpu/drm/radeon/rv770d.h b/drivers/gpu/drm/radeon/rv770d.h
index 162b177a4947496f0f32ecd841caad1ad879696c..6a52b2054f326a76affe0a55fdbc3460cbf9211f 100644 (file)
--- a/drivers/gpu/drm/radeon/rv770d.h
+++ b/drivers/gpu/drm/radeon/rv770d.h
@@ -136,6 +136,11 @@
 #define DMA_TILING_CONFIG                               0x3ec8
 #define DMA_TILING_CONFIG2                              0xd0b8
 
+/* RV730 only */
+#define UVD_UDEC_TILING_CONFIG                          0xef40
+#define UVD_UDEC_DB_TILING_CONFIG                       0xef44
+#define UVD_UDEC_DBW_TILING_CONFIG                      0xef48
+
 #define        GC_USER_SHADER_PIPE_CONFIG                      0x8954
 #define                INACTIVE_QD_PIPES(x)                            ((x) << 8)
 #define                INACTIVE_QD_PIPES_MASK                          0x0000FF00

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 465053d461bb611ebc1a76993ffe201b84033d98..e9663200cac7e38ca12f15fdf6c432a6b0dbf1d6 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1769,6 +1769,9 @@ static void si_gpu_init(struct radeon_device *rdev)
        WREG32(HDP_ADDR_CONFIG, gb_addr_config);
        WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
        WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
+       WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
+       WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
+       WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
 
        si_tiling_mode_table_init(rdev);
 

diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index 3a685855c3d8580e78d74994c266d4c4ccce24dc..042b91d6c94156cda9e07d40cb2b734ee6411b57 100644 (file)
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -831,6 +831,9 @@
 /*
  * UVD
  */
+#define UVD_UDEC_ADDR_CONFIG                           0xEF4C
+#define UVD_UDEC_DB_ADDR_CONFIG                                0xEF50
+#define UVD_UDEC_DBW_ADDR_CONFIG                       0xEF54
 #define UVD_RBC_RB_RPTR                                        0xF690
 #define UVD_RBC_RB_WPTR                                        0xF694