return size;
 }
 
+static void stm32_usart_tx_dma_terminate(struct stm32_port *stm32_port)
+{
+       dmaengine_terminate_async(stm32_port->tx_ch);
+       stm32_port->tx_dma_busy = false;
+}
+
+static bool stm32_usart_tx_dma_started(struct stm32_port *stm32_port)
+{
+       /*
+        * We cannot use the function "dmaengine_tx_status" to know the
+        * status of DMA. This function does not show if the "dma complete"
+        * callback of the DMA transaction has been called. So we prefer
+        * to use "tx_dma_busy" flag to prevent dual DMA transaction at the
+        * same time.
+        */
+       return stm32_port->tx_dma_busy;
+}
+
+static bool stm32_usart_tx_dma_enabled(struct stm32_port *stm32_port)
+{
+       const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
+
+       return !!(readl_relaxed(stm32_port->port.membase + ofs->cr3) & USART_CR3_DMAT);
+}
+
 static void stm32_usart_tx_dma_complete(void *arg)
 {
        struct uart_port *port = arg;
        const struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
        unsigned long flags;
 
-       dmaengine_terminate_async(stm32port->tx_ch);
        stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
-       stm32port->tx_dma_busy = false;
+       stm32_usart_tx_dma_terminate(stm32port);
 
        /* Let's see if we have pending data to send */
        spin_lock_irqsave(&port->lock, flags);
        const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
        struct circ_buf *xmit = &port->state->xmit;
 
-       if (stm32_port->tx_dma_busy) {
+       if (stm32_usart_tx_dma_enabled(stm32_port))
                stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
-               stm32_port->tx_dma_busy = false;
-       }
 
        while (!uart_circ_empty(xmit)) {
                /* Check that TDR is empty before filling FIFO */
        struct dma_async_tx_descriptor *desc = NULL;
        unsigned int count, i;
 
-       if (stm32port->tx_dma_busy)
+       if (stm32_usart_tx_dma_started(stm32port)) {
+               if (!stm32_usart_tx_dma_enabled(stm32port))
+                       stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
                return;
-
-       stm32port->tx_dma_busy = true;
+       }
 
        count = uart_circ_chars_pending(xmit);
 
        if (!desc)
                goto fallback_err;
 
+       /*
+        * Set "tx_dma_busy" flag. This flag will be released when
+        * dmaengine_terminate_async will be called. This flag helps
+        * transmit_chars_dma not to start another DMA transaction
+        * if the callback of the previous is not yet called.
+        */
+       stm32port->tx_dma_busy = true;
+
        desc->callback = stm32_usart_tx_dma_complete;
        desc->callback_param = port;
 
        /* Push current DMA TX transaction in the pending queue */
        if (dma_submit_error(dmaengine_submit(desc))) {
                /* dma no yet started, safe to free resources */
-               dmaengine_terminate_async(stm32port->tx_ch);
+               stm32_usart_tx_dma_terminate(stm32port);
                goto fallback_err;
        }
 
        struct circ_buf *xmit = &port->state->xmit;
 
        if (port->x_char) {
-               if (stm32_port->tx_dma_busy)
+               if (stm32_usart_tx_dma_started(stm32_port) &&
+                   stm32_usart_tx_dma_enabled(stm32_port))
                        stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
                writel_relaxed(port->x_char, port->membase + ofs->tdr);
                port->x_char = 0;
                port->icount.tx++;
-               if (stm32_port->tx_dma_busy)
+               if (stm32_usart_tx_dma_started(stm32_port))
                        stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT);
                return;
        }
        const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 
        if (stm32_port->tx_ch) {
-               dmaengine_terminate_async(stm32_port->tx_ch);
+               stm32_usart_tx_dma_terminate(stm32_port);
                stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
-               stm32_port->tx_dma_busy = false;
        }
 }
 
        u32 val, isr;
        int ret;
 
-       if (stm32_port->tx_dma_busy) {
-               dmaengine_terminate_async(stm32_port->tx_ch);
+       if (stm32_usart_tx_dma_enabled(stm32_port))
                stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
-       }
+
+       if (stm32_usart_tx_dma_started(stm32_port))
+               stm32_usart_tx_dma_terminate(stm32_port);
 
        /* Disable modem control interrupts */
        stm32_usart_disable_ms(port);
        struct dma_slave_config config;
        int ret;
 
-       stm32port->tx_dma_busy = false;
-
        stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L,
                                               &stm32port->tx_dma_buf,
                                               GFP_KERNEL);