&snowball_key_dev,
        &snowball_sbnet_dev,
        &snowball_gpio_en_3v3_regulator_dev,
-       &u8500_thsens_device,
        &u8500_cpufreq_cooling_device,
 +      &sdi0_regulator,
  };
  
  static void __init mop500_init_machine(void)
 
  #include <asm/cpuidle.h>
  #include <asm/proc-fns.h>
  
+ #include "db8500-regs.h"
+ 
  static atomic_t master = ATOMIC_INIT(0);
  static DEFINE_SPINLOCK(master_lock);
 -static DEFINE_PER_CPU(struct cpuidle_device, ux500_cpuidle_device);
  
  static inline int ux500_enter_idle(struct cpuidle_device *dev,
                                   struct cpuidle_driver *drv, int index)
        .state_count = 2,
  };
  
 -/*
 - * For each cpu, setup the broadcast timer because we will
 - * need to migrate the timers for the states >= ApIdle.
 - */
 -static void ux500_setup_broadcast_timer(void *arg)
 -{
 -      int cpu = smp_processor_id();
 -      clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
 -}
 -
  int __init ux500_idle_init(void)
  {
-         /* Configure wake up reasons */
 -      int ret, cpu;
 -      struct cpuidle_device *device;
 -
+       /* Configure wake up reasons */
        prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) |
                             PRCMU_WAKEUP(ABB));
  
 
        clk_register_clkdev(clk, NULL, "gpio.7");
        clk_register_clkdev(clk, NULL, "gpioblock1");
  
-       clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE,
+       clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
                                BIT(12), 0);
  
-       clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE,
+       clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
                                BIT(0), 0);
 -      clk_register_clkdev(clk, NULL, "fsmc");
 +      clk_register_clkdev(clk, "fsmc", NULL);
 +      clk_register_clkdev(clk, NULL, "smsc911x");
  
-       clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", U8500_CLKRST3_BASE,
+       clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
                                BIT(1), 0);
        clk_register_clkdev(clk, "apb_pclk", "ssp0");
  
 
  obj-$(CONFIG_CLKSRC_DBX500_PRCMU)     += clksrc-dbx500-prcmu.o
  obj-$(CONFIG_ARMADA_370_XP_TIMER)     += time-armada-370-xp.o
  obj-$(CONFIG_ARCH_BCM2835)    += bcm2835_timer.o
+ obj-$(CONFIG_ARCH_MARCO)      += timer-marco.o
  obj-$(CONFIG_ARCH_MXS)                += mxs_timer.o
 -obj-$(CONFIG_SUNXI_TIMER)     += sunxi_timer.o
+ obj-$(CONFIG_ARCH_PRIMA2)     += timer-prima2.o
 +obj-$(CONFIG_SUN4I_TIMER)     += sun4i_timer.o
  obj-$(CONFIG_ARCH_TEGRA)      += tegra20_timer.o
  obj-$(CONFIG_VT8500_TIMER)    += vt8500_timer.o
 +obj-$(CONFIG_ARCH_BCM)                += bcm_kona_timer.o
  
  obj-$(CONFIG_ARM_ARCH_TIMER)          += arm_arch_timer.o
  obj-$(CONFIG_CLKSRC_METAG_GENERIC)    += metag_generic.o