drm/amd/display: Not doing optimize bandwidth if flip pending.

[Why]
In some scenario like 1366x768 VSR enabled connected with a 4K monitor
and playing 4K video in clone mode, underflow will be observed due to
decrease dppclk when previouse surface scan isn't finished

[How]
In this use case, surface flip is switching between 4K and 1366x768,
1366x768 needs smaller dppclk, and when decrease the clk and previous
surface scan is for 4K and scan isn't done, underflow will happen.  Not
doing optimize bandwidth in case of flip pending.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2ffb22177df9d31286029769b3a57d0df70921fe..1a2c2e3dd6d2aea78a4b2a3ea9677b205c02aedc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1360,6 +1360,26 @@ bool dc_commit_state(struct dc *dc, struct dc_state *context)
        return (result == DC_OK);
 }
 
+static bool is_flip_pending_in_pipes(struct dc *dc, struct dc_state *context)
+{
+       int i;
+       struct pipe_ctx *pipe;
+
+       for (i = 0; i < MAX_PIPES; i++) {
+               pipe = &context->res_ctx.pipe_ctx[i];
+
+               if (!pipe->plane_state)
+                       continue;
+
+               /* Must set to false to start with, due to OR in update function */
+               pipe->plane_state->status.is_flip_pending = false;
+               dc->hwss.update_pending_status(pipe);
+               if (pipe->plane_state->status.is_flip_pending)
+                       return true;
+       }
+       return false;
+}
+
 bool dc_post_update_surfaces_to_stream(struct dc *dc)
 {
        int i;
@@ -1370,6 +1390,9 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc)
 
        post_surface_trace(dc);
 
+       if (is_flip_pending_in_pipes(dc, context))
+               return true;
+
        for (i = 0; i < dc->res_pool->pipe_count; i++)
                if (context->res_ctx.pipe_ctx[i].stream == NULL ||
                    context->res_ctx.pipe_ctx[i].plane_state == NULL) {