ARM: dts: Configure interconnect target module for omap5 emif

We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" property to avoid new boot
time warnings. The legacy property will be removed in later patches
together with the legacy platform data.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index a571a45561ad81e5f73aa99ce8adf797ce44aba9..823a59aba286178681e2ca74a041e1d424c14fe2 100644 (file)
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -266,28 +266,50 @@
                        };
                };
 
-               emif1: emif@4c000000 {
-                       compatible      = "ti,emif-4d5";
-                       ti,hwmods       = "emif1";
-                       ti,no-idle-on-init;
-                       phy-type        = <2>; /* DDR PHY type: Intelli PHY */
-                       reg = <0x4c000000 0x400>;
-                       interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-                       hw-caps-read-idle-ctrl;
-                       hw-caps-ll-interface;
-                       hw-caps-temp-alert;
+               target-module@4c000000 {
+                       compatible = "ti,sysc-omap4-simple", "ti,sysc";
+                       ti,hwmods = "emif1";
+                       reg = <0x4c000000 0x4>;
+                       reg-names = "rev";
+                       clocks = <&emif_clkctrl OMAP5_EMIF1_CLKCTRL 0>;
+                       clock-names = "fck";
+                       ti,no-idle;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x4c000000 0x1000000>;
+
+                       emif1: emif@0 {
+                               compatible = "ti,emif-4d5";
+                               reg = <0 0x400>;
+                               interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+                               phy-type = <2>; /* DDR PHY type: Intelli PHY */
+                               hw-caps-read-idle-ctrl;
+                               hw-caps-ll-interface;
+                               hw-caps-temp-alert;
+                       };
                };
 
-               emif2: emif@4d000000 {
-                       compatible      = "ti,emif-4d5";
-                       ti,hwmods       = "emif2";
-                       ti,no-idle-on-init;
-                       phy-type        = <2>; /* DDR PHY type: Intelli PHY */
-                       reg = <0x4d000000 0x400>;
-                       interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-                       hw-caps-read-idle-ctrl;
-                       hw-caps-ll-interface;
-                       hw-caps-temp-alert;
+               target-module@4d000000 {
+                       compatible = "ti,sysc-omap4-simple", "ti,sysc";
+                       ti,hwmods = "emif2";
+                       reg = <0x4d000000 0x4>;
+                       reg-names = "rev";
+                       clocks = <&emif_clkctrl OMAP5_EMIF2_CLKCTRL 0>;
+                       clock-names = "fck";
+                       ti,no-idle;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x4d000000 0x1000000>;
+
+                       emif2: emif@0 {
+                               compatible = "ti,emif-4d5";
+                               reg = <0 0x400>;
+                               interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+                               phy-type = <2>; /* DDR PHY type: Intelli PHY */
+                               hw-caps-read-idle-ctrl;
+                               hw-caps-ll-interface;
+                               hw-caps-temp-alert;
+                       };
                };
 
                aes1_target: target-module@4b501000 {