drm/amd/display: STREAM_MAPPER_CONTROL register offset on DCN35

[Why]
The STREAM_MAPPER_CONTROL register offset was left uninitialized,
causing warning in the driver log at runtime

[How]
A temporary solution to add it into dcn35_create_resource_pool.

[TODO]
Remove duplication between SE_DCN35_REG_LIST_RI in dcn35_resource.h and
SE_DCN35_REG_LIST in dcn35_dio_stream_encoder.h

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Artem Grishin <artem.grishin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.h
index 00e2216b62055b2e9bf6b6611fcf784c6cfe96f5..5ec70d46a38fad1b65ddc31cdb2d11d8c28c53b8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.h
@@ -137,7 +137,8 @@ struct resource_pool *dcn35_create_resource_pool(
        SRI_ARR(DIG_FE_EN_CNTL, DIG, id), \
        SRI_ARR(DIG_FE_CLK_CNTL, DIG, id), \
        SRI_ARR(DIG_CLOCK_PATTERN, DIG, id), \
-       SRI_ARR(DIG_FIFO_CTRL0, DIG, id)
+       SRI_ARR(DIG_FIFO_CTRL0, DIG, id), \
+       SRI_ARR(STREAM_MAPPER_CONTROL, DIG, id)
 
 #define LE_DCN35_REG_LIST_RI(id)\
        LE_DCN3_REG_LIST_RI(id),\