perf arm_spe: Refine memory level filling

This commit introduces macros for detecting cache level and cache miss.

Populates the 'mem_lvl_num' field which is a later added attribute for
representing memory level. Set NA ("not available") to memory levels if
memory hierarchy info is absent.

Reviewed-by: James Clark <james.clark@linaro.org>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ali Saidi <alisaidi@amazon.com>
Cc: German Gomez <german.gomez@arm.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
index 24968fc15693e4e6dcbe67dcdc85a261e0f701b7..255a36ecd7bcd89a65ff1ef4a14191ebe76ae9a6 100644 (file)
--- a/tools/perf/util/arm-spe.c
+++ b/tools/perf/util/arm-spe.c
@@ -39,6 +39,15 @@
 
 #define is_ldst_op(op)         (!!((op) & ARM_SPE_OP_LDST))
 
+#define ARM_SPE_CACHE_EVENT(lvl) \
+       (ARM_SPE_##lvl##_ACCESS | ARM_SPE_##lvl##_MISS)
+
+#define arm_spe_is_cache_level(type, lvl) \
+       ((type) & ARM_SPE_CACHE_EVENT(lvl))
+
+#define arm_spe_is_cache_miss(type, lvl) \
+       ((type) & ARM_SPE_##lvl##_MISS)
+
 struct arm_spe {
        struct auxtrace                 auxtrace;
        struct auxtrace_queues          queues;
@@ -813,20 +822,21 @@ static const struct data_source_handle data_source_handles[] = {
 static void arm_spe__synth_memory_level(const struct arm_spe_record *record,
                                        union perf_mem_data_src *data_src)
 {
-       if (record->type & (ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS)) {
+       if (arm_spe_is_cache_level(record->type, LLC)) {
                data_src->mem_lvl = PERF_MEM_LVL_L3;
-
-               if (record->type & ARM_SPE_LLC_MISS)
-                       data_src->mem_lvl |= PERF_MEM_LVL_MISS;
-               else
-                       data_src->mem_lvl |= PERF_MEM_LVL_HIT;
-       } else if (record->type & (ARM_SPE_L1D_ACCESS | ARM_SPE_L1D_MISS)) {
+               data_src->mem_lvl |= arm_spe_is_cache_miss(record->type, LLC) ?
+                                    PERF_MEM_LVL_MISS : PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_L3;
+       } else if (arm_spe_is_cache_level(record->type, L1D)) {
                data_src->mem_lvl = PERF_MEM_LVL_L1;
+               data_src->mem_lvl |= arm_spe_is_cache_miss(record->type, L1D) ?
+                                    PERF_MEM_LVL_MISS : PERF_MEM_LVL_HIT;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_L1;
+       }
 
-               if (record->type & ARM_SPE_L1D_MISS)
-                       data_src->mem_lvl |= PERF_MEM_LVL_MISS;
-               else
-                       data_src->mem_lvl |= PERF_MEM_LVL_HIT;
+       if (!data_src->mem_lvl) {
+               data_src->mem_lvl = PERF_MEM_LVL_NA;
+               data_src->mem_lvl_num = PERF_MEM_LVLNUM_NA;
        }
 
        if (record->type & ARM_SPE_REMOTE_ACCESS)