KVM: arm64: Handle TSB CSYNC traps

The architecture introduces a trap for TSB CSYNC that fits in
the same EC as LS64 and PSB CSYNC. Let's deal with it in a similar
way.

It's not that we expect this to be useful any time soon anyway.

Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h
index ef5a14276ce15daf5c79ac411e54e0233f401478..6079e23608a23b62c89e6956118969a299fe03d9 100644 (file)
--- a/arch/arm64/include/asm/esr.h
+++ b/arch/arm64/include/asm/esr.h
@@ -182,10 +182,11 @@
 #define ESR_ELx_WFx_ISS_WFE    (UL(1) << 0)
 #define ESR_ELx_xVC_IMM_MASK   ((UL(1) << 16) - 1)
 
-/* ISS definitions for LD64B/ST64B/PSBCSYNC instructions */
+/* ISS definitions for LD64B/ST64B/{T,P}SBCSYNC instructions */
 #define ESR_ELx_ISS_OTHER_ST64BV       (0)
 #define ESR_ELx_ISS_OTHER_ST64BV0      (1)
 #define ESR_ELx_ISS_OTHER_LDST64B      (2)
+#define ESR_ELx_ISS_OTHER_TSBCSYNC     (3)
 #define ESR_ELx_ISS_OTHER_PSBCSYNC     (4)
 
 #define DISR_EL1_IDS           (UL(1) << 24)

diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 9b5a875ad2222c48c33f40266d76fe264057f016..923c1edb7463d15fa409afed40cba41bd6221d69 100644 (file)
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -2044,6 +2044,7 @@ static const union trap_config non_0x18_fgt[] __initconst = {
        FGT(HFGITR, SVC_EL1, 1),
        FGT(HFGITR, SVC_EL0, 1),
        FGT(HFGITR, ERET, 1),
+       FGT(HFGITR2, TSBCSYNC, 1),
 };
 
 static union trap_config get_trap_config(u32 sysreg)

diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index cc44ee56e512be35a1ce0ba943c462d708ccd70d..60507ad8b86f881be79e00527003965ab2c76fc5 100644 (file)
--- a/arch/arm64/kvm/handle_exit.c
+++ b/arch/arm64/kvm/handle_exit.c
@@ -347,6 +347,11 @@ static int handle_other(struct kvm_vcpu *vcpu)
                if (is_l2)
                        fwd = !(hcrx & HCRX_EL2_EnALS);
                break;
+       case ESR_ELx_ISS_OTHER_TSBCSYNC:
+               allowed = kvm_has_feat(kvm, ID_AA64DFR0_EL1, TraceBuffer, TRBE_V1P1);
+               if (is_l2)
+                       fwd = (__vcpu_sys_reg(vcpu, HFGITR2_EL2) & HFGITR2_EL2_TSBCSYNC);
+               break;
        case ESR_ELx_ISS_OTHER_PSBCSYNC:
                allowed = kvm_has_feat(kvm, ID_AA64DFR0_EL1, PMSVer, V1P5);
                if (is_l2)