if (!mul)
                div = CDCE706_DIVIDER_DIVIDER_MAX;
 
-       if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+       if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
                unsigned long best_diff = rate;
                unsigned long best_div = 0;
                struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0].parent];
 
                   mux_hw && mux_ops && mux_ops->set_parent) {
                req->best_parent_hw = NULL;
 
-               if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) {
+               if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
                        parent = clk_get_parent(mux_hw->clk);
                        req->best_parent_hw = __clk_get_hw(parent);
                        req->best_parent_rate = __clk_get_rate(parent);
 
 
        maxdiv = _get_maxdiv(table, width, flags);
 
-       if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
+       if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
                parent_rate = *best_parent_rate;
                bestdiv = _div_round(table, parent_rate, rate, flags);
                bestdiv = bestdiv == 0 ? 1 : bestdiv;
 
 {
        struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
 
-       if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+       if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
                unsigned long best_parent;
 
                best_parent = (rate / fix->mult) * fix->div;
 
                divby4 = 1;
 
        /* multisync can set pll */
-       if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) {
+       if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
                /*
                 * find largest integer divider for max
                 * vco frequency and given target rate
                rate = SI5351_CLKOUT_MIN_FREQ;
 
        /* request frequency if multisync master */
-       if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) {
+       if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
                /* use r divider for frequencies below 1MHz */
                rdiv = SI5351_OUTPUT_CLK_DIV_1;
                while (rate < SI5351_MULTISYNTH_MIN_FREQ &&
 
        if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
                mult = 2;
 
-       if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+       if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
                unsigned long best_parent = rate / mult;
 
                *prate =
 
        if (index < 0)
                return index;
 
-       clk_flags = __clk_get_flags(hw->clk);
+       clk_flags = clk_hw_get_flags(hw);
        p = clk_get_parent_by_index(hw->clk, index);
        if (clk_flags & CLK_SET_RATE_PARENT) {
                rate = rate * f->pre_div;
 
        if (index < 0)
                return index;
 
-       clk_flags = __clk_get_flags(hw->clk);
+       clk_flags = clk_hw_get_flags(hw);
        p = clk_get_parent_by_index(hw->clk, index);
        if (clk_flags & CLK_SET_RATE_PARENT) {
                if (f->pre_div) {
 
        /* Round div according to exact prate and wished rate */
        div = clk_best_div(*prate, rate);
 
-       if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
+       if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
                *prate = rate * div;
                return rate;
        }
 
                parent = clk_get_parent_by_index(clk, i);
                if (!parent)
                        continue;
-               if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
+               if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
                        parent_rate = __clk_round_rate(parent, req->rate);
                else
                        parent_rate = __clk_get_rate(parent);
 
                parent = clk_get_parent_by_index(clk, i);
                if (!parent)
                        continue;
-               if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
+               if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
                        parent_rate = __clk_round_rate(parent, req->rate);
                else
                        parent_rate = __clk_get_rate(parent);
 
        if (!IS_ERR(clk)) {
                setup->clk = clk;
                if (setup->clkdm_name) {
-                       if (__clk_get_flags(clk) & CLK_IS_BASIC) {
+                       clk_hw = __clk_get_hw(clk);
+                       if (clk_hw_get_flags(clk_hw) & CLK_IS_BASIC) {
                                pr_warn("can't setup clkdm for basic clk %s\n",
                                        setup->name);
                        } else {
-                               clk_hw = __clk_get_hw(clk);
                                to_clk_hw_omap(clk_hw)->clkdm_name =
                                        setup->clkdm_name;
                                omap2_init_clk_clkdm(clk_hw);
 
                               __func__, node->full_name, i, PTR_ERR(clk));
                        continue;
                }
-               if (__clk_get_flags(clk) & CLK_IS_BASIC) {
+               clk_hw = __clk_get_hw(clk);
+               if (clk_hw_get_flags(clk_hw) & CLK_IS_BASIC) {
                        pr_warn("can't setup clkdm for basic clk %s\n",
                                __clk_get_name(clk));
                        continue;
                }
-               clk_hw = __clk_get_hw(clk);
                to_clk_hw_omap(clk_hw)->clkdm_name = clkdm_name;
                omap2_init_clk_clkdm(clk_hw);
        }
 
 
        maxdiv = _get_maxdiv(divider);
 
-       if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
+       if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
                parent_rate = *best_parent_rate;
                bestdiv = DIV_ROUND_UP(parent_rate, rate);
                bestdiv = bestdiv == 0 ? 1 : bestdiv;
 
        clk = clk_register(NULL, &clk_hw->hw);
 
        if (!IS_ERR(clk)) {
-               omap2_init_clk_hw_omap_clocks(clk);
+               omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
                of_clk_add_provider(node, of_clk_src_simple_get, clk);
                kfree(clk_hw->hw.init->parent_names);
                kfree(clk_hw->hw.init);
        if (IS_ERR(clk)) {
                kfree(clk_hw);
        } else {
-               omap2_init_clk_hw_omap_clocks(clk);
+               omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
                of_clk_add_provider(node, of_clk_src_simple_get, clk);
        }
 }
 
                do {
                        parent = __clk_get_parent(hw->clk);
                        hw = __clk_get_hw(parent);
-               } while (hw && (__clk_get_flags(hw->clk) & CLK_IS_BASIC));
+               } while (hw && (clk_hw_get_flags(hw) & CLK_IS_BASIC));
                if (!hw)
                        break;
                pclk = to_clk_hw_omap(hw);
 
        if (IS_ERR(clk))
                kfree(clk_hw);
        else
-               omap2_init_clk_hw_omap_clocks(clk);
+               omap2_init_clk_hw_omap_clocks(&clk_hw->hw);
 
        return clk;
 }