#define P3A_RG_XTAL_EXT_EN_U3          GENMASK(11, 10)
 #define P3A_RG_XTAL_EXT_EN_U3_VAL(x)   ((0x3 & (x)) << 10)
 
+#define U3P_U3_PHYD_LFPS1              (SSUSB_SIFSLV_U3PHYD_BASE + 0x000c)
+#define P3D_RG_FWAKE_TH                GENMASK(21, 16)
+#define P3D_RG_FWAKE_TH_VAL(x) ((0x3f & (x)) << 16)
+
 #define U3P_PHYD_CDR1          (SSUSB_SIFSLV_U3PHYD_BASE + 0x005c)
 #define P3D_RG_CDR_BIR_LTD1            GENMASK(28, 24)
 #define P3D_RG_CDR_BIR_LTD1_VAL(x)     ((0x1f & (x)) << 24)
        tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
        writel(tmp, port_base + U3P_PHYD_CDR1);
 
+       tmp = readl(port_base + U3P_U3_PHYD_LFPS1);
+       tmp &= ~P3D_RG_FWAKE_TH;
+       tmp |= P3D_RG_FWAKE_TH_VAL(0x34);
+       writel(tmp, port_base + U3P_U3_PHYD_LFPS1);
+
        tmp = readl(port_base + U3P_U3_PHYD_RXDET1);
        tmp &= ~P3D_RG_RXDET_STB2_SET;
        tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);