clk: exynos5433: remove CLK_IGNORE_UNUSED flag from SPI clocks

Because the Exynos5433 SPI driver supports the ioclk handling and
the following patch:

  http://marc.info/?l=linux-kernel&m=146787645626318&w=2

fixes a synchronus abort issue, none of the SPI clocks require
any critical handling: remove, then, the CLK_IGNORE_UNUSED flag
for the SPI related clocks.

Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1468317736-18841-8-git-send-email-andi.shyti@samsung.com

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 4204eb828d86fc229543b8ee4eaa0634d3f99144..ea1608682d7fe90b3b20ede863386d82c4f23e7b 100644 (file)
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -1661,8 +1661,7 @@ static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
        GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
                        ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
-                       ENABLE_SCLK_PERIC, 12,
-                       CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+                       ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
                        ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
@@ -1677,7 +1676,7 @@ static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
        GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
                        5, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
-                       4, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
+                       4, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
                        3, CLK_SET_RATE_PARENT, 0),
        GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",