drm/amdgpu: Add a noverbose flag to psp_wait_for

For extended wait with retries on a PSP register value, add a noverbose
flag to avoid excessive error messages on each timeout.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Asad Kamal <asad.kamal@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index a4bede28df173de8a4868a28f7576b7779e4c4db..75911600d5047ba5602e0221188785a53cb14c09 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -575,9 +575,11 @@ static int psp_sw_fini(struct amdgpu_ip_block *ip_block)
        return 0;
 }
 
-int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
-                uint32_t reg_val, uint32_t mask, bool check_changed)
+int psp_wait_for(struct psp_context *psp, uint32_t reg_index, uint32_t reg_val,
+                uint32_t mask, uint32_t flags)
 {
+       bool check_changed = flags & PSP_WAITREG_CHANGED;
+       bool verbose = !(flags & PSP_WAITREG_NOVERBOSE);
        uint32_t val;
        int i;
        struct amdgpu_device *adev = psp->adev;
@@ -597,9 +599,10 @@ int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
                udelay(1);
        }
 
-       dev_err(adev->dev,
-               "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x",
-               reg_index, mask, val, reg_val);
+       if (verbose)
+               dev_err(adev->dev,
+                       "psp reg (0x%x) wait timed out, mask: %x, read: %x exp: %x",
+                       reg_index, mask, val, reg_val);
 
        return -ETIME;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 4bc0ec49d2e9d6b855241209c73d2cd610eea3a8..237b624aa51ca31dacc0f0c238f9c146dfa99716 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -134,6 +134,9 @@ enum psp_reg_prog_id {
        PSP_REG_LAST
 };
 
+#define PSP_WAITREG_CHANGED BIT(0) /* check if the value has changed */
+#define PSP_WAITREG_NOVERBOSE BIT(1) /* No error verbose */
+
 struct psp_funcs {
        int (*init_microcode)(struct psp_context *psp);
        int (*wait_for_bootloader)(struct psp_context *psp);
@@ -532,8 +535,8 @@ extern const struct amdgpu_ip_block_version psp_v13_0_ip_block;
 extern const struct amdgpu_ip_block_version psp_v13_0_4_ip_block;
 extern const struct amdgpu_ip_block_version psp_v14_0_ip_block;
 
-extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
-                       uint32_t field_val, uint32_t mask, bool check_changed);
+int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
+                uint32_t field_val, uint32_t mask, uint32_t flags);
 extern int psp_wait_for_spirom_update(struct psp_context *psp, uint32_t reg_index,
                        uint32_t field_val, uint32_t mask, uint32_t msec_timeout);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
index 2c4ebd98927ff384993f95511cc796994b36d200..3584b8c18fd9934475ba7aa91ed3e3380267d598 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
@@ -94,7 +94,7 @@ static int psp_v10_0_ring_create(struct psp_context *psp,
 
        /* Wait for response flag (bit 31) in C2PMSG_64 */
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                          MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                          MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
 
        return ret;
 }
@@ -115,7 +115,7 @@ static int psp_v10_0_ring_stop(struct psp_context *psp,
 
        /* Wait for response flag (bit 31) in C2PMSG_64 */
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                          MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                          MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
 
        return ret;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 1a4a26e6ffd24cbd407d9ef68e382d41a53f7907..6cc05d36e3594de61758da72a6b96c965fb3540e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -152,11 +152,9 @@ static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
        for (retry_loop = 0; retry_loop < 10; retry_loop++) {
                /* Wait for bootloader to signify that is
                    ready having bit 31 of C2PMSG_35 set to 1 */
-               ret = psp_wait_for(psp,
-                                  SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                                  0x80000000,
-                                  0x80000000,
-                                  false);
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+                       0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
 
                if (ret == 0)
                        return 0;
@@ -252,8 +250,8 @@ static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
        /* there might be handshake issue with hardware which needs delay */
        mdelay(20);
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
-                          RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
-                          0, true);
+                          RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,
+                          PSP_WAITREG_CHANGED);
 
        return ret;
 }
@@ -279,11 +277,11 @@ static int psp_v11_0_ring_stop(struct psp_context *psp,
        if (amdgpu_sriov_vf(adev))
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        else
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
 
        return ret;
 }
@@ -321,13 +319,13 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
                /* Wait for response flag (bit 31) in C2PMSG_101 */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
 
        } else {
                /* Wait for sOS ready for ring creation */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                       MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
+                       MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
                if (ret) {
                        DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
                        return ret;
@@ -353,7 +351,7 @@ static int psp_v11_0_ring_create(struct psp_context *psp,
                /* Wait for response flag (bit 31) in C2PMSG_64 */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        }
 
        return ret;
@@ -387,7 +385,7 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp)
        offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 
        ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,
-                          MBOX_TOS_READY_MASK, false);
+                          MBOX_TOS_READY_MASK, 0);
 
        if (ret) {
                DRM_INFO("psp is not working correctly before mode1 reset!\n");
@@ -402,7 +400,7 @@ static int psp_v11_0_mode1_reset(struct psp_context *psp)
        offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 
        ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,
-                          false);
+                          0);
 
        if (ret) {
                DRM_INFO("psp mode 1 reset failed!\n");
@@ -428,8 +426,9 @@ static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
 
        max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
        for (i = 0; i < max_wait; i++) {
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                                  0x80000000, 0x80000000, false);
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
+                       0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
                if (ret == 0)
                        break;
        }
@@ -608,7 +607,7 @@ static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                            0x80000000, 0x80000000, false);
+                          0x80000000, 0x80000000, 0);
        if (ret)
                return ret;
 
@@ -645,7 +644,7 @@ static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                                    0x80000000, 0x80000000, false);
+                          0x80000000, 0x80000000, 0);
        if (!ret)
                *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c
index 338d015c0f2ee266c72f9b754f4551bf608376db..93787a90d598b9266b204ecef34c6863f3e00862 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.c
@@ -43,7 +43,7 @@ static int psp_v11_0_8_ring_stop(struct psp_context *psp,
                /* Wait for response flag (bit 31) */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        } else {
                /* Write the ring destroy command*/
                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
@@ -53,7 +53,7 @@ static int psp_v11_0_8_ring_stop(struct psp_context *psp,
                /* Wait for response flag (bit 31) */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        }
 
        return ret;
@@ -91,13 +91,13 @@ static int psp_v11_0_8_ring_create(struct psp_context *psp,
                /* Wait for response flag (bit 31) in C2PMSG_101 */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
 
        } else {
                /* Wait for sOS ready for ring creation */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                       MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
+                       MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
                if (ret) {
                        DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
                        return ret;
@@ -123,7 +123,7 @@ static int psp_v11_0_8_ring_create(struct psp_context *psp,
                /* Wait for response flag (bit 31) in C2PMSG_64 */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        }
 
        return ret;

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
index d54b3e0fabaf4064d69c2f67a429a3bfbed740f1..4c6450d62299aa942b5404720eda4a26d94c9072 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v12_0.c
@@ -82,7 +82,7 @@ static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
 
        /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                          0x80000000, 0x80000000, false);
+                          0x80000000, 0x80000000, 0);
        if (ret)
                return ret;
 
@@ -97,7 +97,7 @@ static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
               psp_gfxdrv_command_reg);
 
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                          0x80000000, 0x80000000, false);
+                          0x80000000, 0x80000000, 0);
 
        return ret;
 }
@@ -118,7 +118,7 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
 
        /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                          0x80000000, 0x80000000, false);
+                          0x80000000, 0x80000000, 0);
        if (ret)
                return ret;
 
@@ -133,8 +133,8 @@ static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
               psp_gfxdrv_command_reg);
 
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
-                          RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
-                          0, true);
+                          RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,
+                          PSP_WAITREG_CHANGED);
 
        return ret;
 }
@@ -163,7 +163,7 @@ static int psp_v12_0_ring_create(struct psp_context *psp,
 
        /* Wait for response flag (bit 31) in C2PMSG_64 */
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                          MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                          MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
 
        return ret;
 }
@@ -186,11 +186,11 @@ static int psp_v12_0_ring_stop(struct psp_context *psp,
        if (amdgpu_sriov_vf(adev))
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        else
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
 
        return ret;
 }
@@ -222,7 +222,7 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp)
        offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 
        ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,
-                          MBOX_TOS_READY_MASK, false);
+                          MBOX_TOS_READY_MASK, 0);
 
        if (ret) {
                DRM_INFO("psp is not working correctly before mode1 reset!\n");
@@ -237,7 +237,7 @@ static int psp_v12_0_mode1_reset(struct psp_context *psp)
        offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 
        ret = psp_wait_for(psp, offset, MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK,
-                          false);
+                          0);
 
        if (ret) {
                DRM_INFO("psp mode 1 reset failed!\n");

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 58b6b64dcd683bd693a0d06655bbb6b001b65fe2..af4a7d7c4abd8d3c7f71c27b5190bac37695f8c0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -182,7 +182,7 @@ static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
                   ready having bit 31 of C2PMSG_33 set to 1 */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),
-                       0x80000000, 0xffffffff, false);
+                       0x80000000, 0xffffffff, PSP_WAITREG_NOVERBOSE);
 
                if (ret == 0)
                        break;
@@ -213,7 +213,7 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
        for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) {
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
-                       0x80000000, 0xffffffff, false);
+                       0x80000000, 0xffffffff, PSP_WAITREG_NOVERBOSE);
 
                if (ret == 0)
                        return 0;
@@ -362,8 +362,8 @@ static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
        /* there might be handshake issue with hardware which needs delay */
        mdelay(20);
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
-                          RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
-                          0, true);
+                          RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0,
+                          PSP_WAITREG_CHANGED);
 
        if (!ret)
                psp_v13_0_init_sos_version(psp);
@@ -386,7 +386,7 @@ static int psp_v13_0_ring_stop(struct psp_context *psp,
                /* Wait for response flag (bit 31) */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        } else {
                /* Write the ring destroy command*/
                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
@@ -396,7 +396,7 @@ static int psp_v13_0_ring_stop(struct psp_context *psp,
                /* Wait for response flag (bit 31) */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        }
 
        return ret;
@@ -434,13 +434,13 @@ static int psp_v13_0_ring_create(struct psp_context *psp,
                /* Wait for response flag (bit 31) in C2PMSG_101 */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
 
        } else {
                /* Wait for sOS ready for ring creation */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
-                       MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
+                       MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
                if (ret) {
                        DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
                        return ret;
@@ -466,7 +466,7 @@ static int psp_v13_0_ring_create(struct psp_context *psp,
                /* Wait for response flag (bit 31) in C2PMSG_64 */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        }
 
        return ret;
@@ -529,8 +529,9 @@ static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
 
        max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
        for (i = 0; i < max_wait; i++) {
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
-                                  0x80000000, 0x80000000, false);
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
+                       0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
                if (ret == 0)
                        break;
        }
@@ -682,7 +683,7 @@ static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc
        WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
-                            0x80000000, 0x80000000, false);
+                          0x80000000, 0x80000000, 0);
        if (ret)
                return ret;
 
@@ -719,7 +720,7 @@ static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
        WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
-                                    0x80000000, 0x80000000, false);
+                          0x80000000, 0x80000000, 0);
        if (!ret)
                *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
 
@@ -744,8 +745,9 @@ static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
                ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
                                                 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
        else
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
-                                  MBOX_READY_FLAG, MBOX_READY_MASK, false);
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
+                       MBOX_READY_FLAG, MBOX_READY_MASK, 0);
        if (ret) {
                dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
                return ret;
@@ -769,7 +771,7 @@ static int psp_v13_0_update_spirom(struct psp_context *psp,
 
        /* Confirm PSP is ready to start */
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
-                          MBOX_READY_FLAG, MBOX_READY_MASK, false);
+                          MBOX_READY_FLAG, MBOX_READY_MASK, 0);
        if (ret) {
                dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
                return ret;
@@ -804,7 +806,7 @@ static int psp_v13_0_dump_spirom(struct psp_context *psp,
 
        /* Confirm PSP is ready to start */
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
-                          MBOX_READY_FLAG, MBOX_READY_MASK, false);
+                          MBOX_READY_FLAG, MBOX_READY_MASK, 0);
        if (ret) {
                dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
                return ret;
@@ -931,8 +933,9 @@ static int psp_v13_0_reg_program_no_ring(struct psp_context *psp, uint32_t val,
                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, id);
                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, val);
 
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
-                                  0x80000000, 0x80000000, false);
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
+                       0x80000000, 0x80000000, 0);
        }
 
        return ret;

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
index f65af52c1c193989994b85b781cf613be08092eb..5f39a2edcc9562776e877317b101830d75c6a82d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.c
@@ -76,11 +76,9 @@ static int psp_v13_0_4_wait_for_bootloader(struct psp_context *psp)
        for (retry_loop = 0; retry_loop < 10; retry_loop++) {
                /* Wait for bootloader to signify that is
                    ready having bit 31 of C2PMSG_35 set to 1 */
-               ret = psp_wait_for(psp,
-                                  SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
-                                  0x80000000,
-                                  0x80000000,
-                                  false);
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
+                       0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
 
                if (ret == 0)
                        return 0;
@@ -185,8 +183,8 @@ static int psp_v13_0_4_bootloader_load_sos(struct psp_context *psp)
        /* there might be handshake issue with hardware which needs delay */
        mdelay(20);
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
-                          RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
-                          0, true);
+                          RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0,
+                          PSP_WAITREG_CHANGED);
 
        return ret;
 }
@@ -206,7 +204,7 @@ static int psp_v13_0_4_ring_stop(struct psp_context *psp,
                /* Wait for response flag (bit 31) */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        } else {
                /* Write the ring destroy command*/
                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
@@ -216,7 +214,7 @@ static int psp_v13_0_4_ring_stop(struct psp_context *psp,
                /* Wait for response flag (bit 31) */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        }
 
        return ret;
@@ -254,13 +252,13 @@ static int psp_v13_0_4_ring_create(struct psp_context *psp,
                /* Wait for response flag (bit 31) in C2PMSG_101 */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
 
        } else {
                /* Wait for sOS ready for ring creation */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
-                       MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
+                       MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
                if (ret) {
                        DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
                        return ret;
@@ -286,7 +284,7 @@ static int psp_v13_0_4_ring_create(struct psp_context *psp,
                /* Wait for response flag (bit 31) in C2PMSG_64 */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        }
 
        return ret;

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
index ffa47c7d24c919c8f1f5b73cafa4d8c473c37f46..36ef4a72ad1d56139dd54afe85fe49c5103e9516 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v14_0.c
@@ -109,11 +109,9 @@ static int psp_v14_0_wait_for_bootloader(struct psp_context *psp)
        for (retry_loop = 0; retry_loop < 10; retry_loop++) {
                /* Wait for bootloader to signify that is
                    ready having bit 31 of C2PMSG_35 set to 1 */
-               ret = psp_wait_for(psp,
-                                  SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
-                                  0x80000000,
-                                  0x80000000,
-                                  false);
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
+                       0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
 
                if (ret == 0)
                        return 0;
@@ -228,9 +226,10 @@ static int psp_v14_0_bootloader_load_sos(struct psp_context *psp)
 
        /* there might be handshake issue with hardware which needs delay */
        mdelay(20);
-       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81),
-                          RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81),
-                          0, true);
+       ret = psp_wait_for(psp,
+                          SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81),
+                          RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81), 0,
+                          PSP_WAITREG_CHANGED);
 
        return ret;
 }
@@ -250,7 +249,7 @@ static int psp_v14_0_ring_stop(struct psp_context *psp,
                /* Wait for response flag (bit 31) */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        } else {
                /* Write the ring destroy command*/
                WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
@@ -260,7 +259,7 @@ static int psp_v14_0_ring_stop(struct psp_context *psp,
                /* Wait for response flag (bit 31) */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        }
 
        return ret;
@@ -298,13 +297,13 @@ static int psp_v14_0_ring_create(struct psp_context *psp,
                /* Wait for response flag (bit 31) in C2PMSG_101 */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
 
        } else {
                /* Wait for sOS ready for ring creation */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
-                       MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, false);
+                       MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
                if (ret) {
                        DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
                        return ret;
@@ -330,7 +329,7 @@ static int psp_v14_0_ring_create(struct psp_context *psp,
                /* Wait for response flag (bit 31) in C2PMSG_64 */
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
-                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, false);
+                       MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
        }
 
        return ret;
@@ -393,8 +392,9 @@ static int psp_v14_0_memory_training_send_msg(struct psp_context *psp, int msg)
 
        max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
        for (i = 0; i < max_wait; i++) {
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
-                                  0x80000000, 0x80000000, false);
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
+                       0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
                if (ret == 0)
                        break;
        }
@@ -545,8 +545,9 @@ static int psp_v14_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc
         */
        WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 
-       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
-                            0x80000000, 0x80000000, false);
+       ret = psp_wait_for(psp,
+                          SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
+                          0x80000000, 0x80000000, 0);
        if (ret)
                return ret;
 
@@ -582,8 +583,9 @@ static int psp_v14_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 
        WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 
-       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
-                                    0x80000000, 0x80000000, false);
+       ret = psp_wait_for(psp,
+                          SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
+                          0x80000000, 0x80000000, 0);
        if (!ret)
                *fw_ver = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36);
 
@@ -607,11 +609,13 @@ static int psp_v14_0_exec_spi_cmd(struct psp_context *psp, int cmd)
                ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
                                                 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
        else
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
-                                  MBOX_READY_FLAG, MBOX_READY_MASK, false);
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
+                       MBOX_READY_FLAG, MBOX_READY_MASK, 0);
 
-       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
-                               MBOX_READY_FLAG, MBOX_READY_MASK, false);
+       ret = psp_wait_for(psp,
+                          SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
+                          MBOX_READY_FLAG, MBOX_READY_MASK, 0);
        if (ret) {
                dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
                return ret;
@@ -634,8 +638,9 @@ static int psp_v14_0_update_spirom(struct psp_context *psp,
        int ret;
 
        /* Confirm PSP is ready to start */
-       ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
-                          MBOX_READY_FLAG, MBOX_READY_MASK, false);
+       ret = psp_wait_for(psp,
+                          SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
+                          MBOX_READY_FLAG, MBOX_READY_MASK, 0);
        if (ret) {
                dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
                return ret;

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
index f6b75e3e47ffb856de071fb2800aac69ec782ceb..833830bc3e2e30019a89b4dd47bf07be7a6b41cd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
@@ -91,7 +91,7 @@ static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
 
        /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                          0x80000000, 0x80000000, false);
+                          0x80000000, 0x80000000, 0);
        if (ret)
                return ret;
 
@@ -109,7 +109,7 @@ static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
        mdelay(20);
 
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                          0x80000000, 0x80000000, false);
+                          0x80000000, 0x80000000, 0);
 
        return ret;
 }
@@ -130,7 +130,7 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
 
        /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
-                          0x80000000, 0x80000000, false);
+                          0x80000000, 0x80000000, 0);
        if (ret)
                return ret;
 
@@ -147,8 +147,8 @@ static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
        /* there might be handshake issue with hardware which needs delay */
        mdelay(20);
        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
-                          RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
-                          0, true);
+                          RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,
+                          PSP_WAITREG_CHANGED);
        return ret;
 }
 
@@ -168,7 +168,7 @@ static void psp_v3_1_reroute_ih(struct psp_context *psp)
 
        mdelay(20);
        psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                    0x80000000, 0x8000FFFF, false);
+                    0x80000000, 0x8000FFFF, 0);
 
        /* Change IH ring for UMC */
        tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
@@ -180,7 +180,7 @@ static void psp_v3_1_reroute_ih(struct psp_context *psp)
 
        mdelay(20);
        psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                    0x80000000, 0x8000FFFF, false);
+                    0x80000000, 0x8000FFFF, 0);
 }
 
 static int psp_v3_1_ring_create(struct psp_context *psp,
@@ -217,9 +217,9 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
                mdelay(20);
 
                /* Wait for response flag (bit 31) in C2PMSG_101 */
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
-                                       mmMP0_SMN_C2PMSG_101), 0x80000000,
-                                       0x8000FFFF, false);
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
+                       0x80000000, 0x8000FFFF, 0);
        } else {
 
                /* Write low address of the ring to C2PMSG_69 */
@@ -240,10 +240,9 @@ static int psp_v3_1_ring_create(struct psp_context *psp,
                mdelay(20);
 
                /* Wait for response flag (bit 31) in C2PMSG_64 */
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0,
-                                       mmMP0_SMN_C2PMSG_64), 0x80000000,
-                                       0x8000FFFF, false);
-
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+                       0x80000000, 0x8000FFFF, 0);
        }
        return ret;
 }
@@ -267,11 +266,13 @@ static int psp_v3_1_ring_stop(struct psp_context *psp,
 
        /* Wait for response flag (bit 31) */
        if (amdgpu_sriov_vf(adev))
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
-                                  0x80000000, 0x80000000, false);
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
+                       0x80000000, 0x80000000, 0);
        else
-               ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
-                                  0x80000000, 0x80000000, false);
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
+                       0x80000000, 0x80000000, 0);
 
        return ret;
 }
@@ -311,7 +312,7 @@ static int psp_v3_1_mode1_reset(struct psp_context *psp)
 
        offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 
-       ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
+       ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, 0);
 
        if (ret) {
                DRM_INFO("psp is not working correctly before mode1 reset!\n");
@@ -325,7 +326,7 @@ static int psp_v3_1_mode1_reset(struct psp_context *psp)
 
        offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 
-       ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
+       ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, 0);
 
        if (ret) {
                DRM_INFO("psp mode 1 reset failed!\n");