Use the proper accessors instead of open access to irq_desc.
Converted with coccinelle.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
                        smp_wmb();
 
                        /* Clear norequest flags */
-                       irq_to_desc(i)->status &= ~IRQ_NOREQUEST;
+                       irq_clear_status_flags(i, IRQ_NOREQUEST);
 
                        /* Legacy flags are left to default at this point,
                         * one can then use irq_create_mapping() to
 
                if (!chip)
                        continue;
 
-               if (chip->irq_eoi && desc->status & IRQ_INPROGRESS)
+               if (chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data))
                        chip->irq_eoi(&desc->irq_data);
 
                if (chip->irq_mask)
                        chip->irq_mask(&desc->irq_data);
 
-               if (chip->irq_disable && !(desc->status & IRQ_DISABLED))
+               if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data))
                        chip->irq_disable(&desc->irq_data);
        }
 }
 
 cpld_pic_host_map(struct irq_host *h, unsigned int virq,
                             irq_hw_number_t hw)
 {
-       irq_to_desc(virq)->status |= IRQ_LEVEL;
+       irq_set_status_flags(virq, IRQ_LEVEL);
        set_irq_chip_and_handler(virq, &cpld_pic, handle_level_irq);
        return 0;
 }
 
        /* Processing done; can reenable the cascade now */
        raw_spin_lock(&desc->lock);
        chip->irq_ack(&desc->irq_data);
-       if (!(desc->status & IRQ_DISABLED))
+       if (!irqd_irq_disabled(&desc->irq_data))
                chip->irq_unmask(&desc->irq_data);
        raw_spin_unlock(&desc->lock);
 }
 
 static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
                            irq_hw_number_t hw)
 {
-       irq_to_desc(virq)->status |= IRQ_LEVEL;
+       irq_set_status_flags(virq, IRQ_LEVEL);
        set_irq_chip_data(virq, h->host_data);
        set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
        return 0;
 
                irq_hw_number_t hwirq)
 {
        /* All interrupts are LEVEL sensitive */
-       irq_to_desc(virq)->status |= IRQ_LEVEL;
+       irq_set_status_flags(virq, IRQ_LEVEL);
        set_irq_chip_and_handler(virq, &socrates_fpga_pic_chip,
                        handle_fasteoi_irq);
 
 
                          irq_hw_number_t hwirq)
 {
        /* All interrupts are LEVEL sensitive */
-       irq_to_desc(virq)->status |= IRQ_LEVEL;
+       irq_set_status_flags(virq, IRQ_LEVEL);
        set_irq_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
 
        return 0;
 
 static int beatic_pic_host_map(struct irq_host *h, unsigned int virq,
                               irq_hw_number_t hw)
 {
-       struct irq_desc *desc = irq_to_desc(virq);
        int64_t err;
 
        err = beat_construct_and_connect_irq_plug(virq, hw);
        if (err < 0)
                return -EIO;
 
-       desc->status |= IRQ_LEVEL;
+       irq_set_status_flags(virq, IRQ_LEVEL);
        set_irq_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq);
        return 0;
 }
 
                           irq_hw_number_t hwirq)
 {
        set_irq_chip_data(virq, h->host_data);
-       irq_to_desc(virq)->status |= IRQ_LEVEL;
+       irq_set_status_flags(virq, IRQ_LEVEL);
        set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq);
        return 0;
 }
 
                           irq_hw_number_t hwirq)
 {
        set_irq_chip_data(virq, h->host_data);
-       irq_to_desc(virq)->status |= IRQ_LEVEL;
+       irq_set_status_flags(virq, IRQ_LEVEL);
        set_irq_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
        return 0;
 }
 
        raw_spin_lock(&desc->lock);
        chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */
-       if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
+       if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask)
                chip->irq_unmask(&desc->irq_data);
        raw_spin_unlock(&desc->lock);
 }
 
 static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
                             irq_hw_number_t hw)
 {
-       struct irq_desc *desc = irq_to_desc(virq);
        int level;
 
        if (hw >= max_irqs)
         */
        level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f)));
        if (level)
-               desc->status |= IRQ_LEVEL;
+               irq_set_status_flags(virq, IRQ_LEVEL);
        set_irq_chip_and_handler(virq, &pmac_pic, level ?
                                 handle_level_irq : handle_edge_irq);
        return 0;
 
        /* Insert the interrupt mapping into the radix tree for fast lookup */
        irq_radix_revmap_insert(xics_host, virq, hw);
 
-       irq_to_desc(virq)->status |= IRQ_LEVEL;
+       irq_set_status_flags(virq, IRQ_LEVEL);
        set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
        return 0;
 }
 
 {
        pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
 
-       irq_to_desc(virq)->status |= IRQ_LEVEL;
+       irq_set_status_flags(virq, IRQ_LEVEL);
        set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
        return 0;
 }
 
 {
        pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
 
-       irq_to_desc(virq)->status |= IRQ_LEVEL;
+       irq_set_status_flags(virq, IRQ_LEVEL);
        set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
        return 0;
 }
 
        struct fsl_msi *msi_data = h->host_data;
        struct irq_chip *chip = &fsl_msi_chip;
 
-       irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
+       irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
 
        set_irq_chip_data(virq, msi_data);
        set_irq_chip_and_handler(virq, chip, handle_edge_irq);
 
 
        /* We block the internal cascade */
        if (hw == 2)
-               irq_to_desc(virq)->status |= IRQ_NOREQUEST;
+               irq_set_status_flags(virq, IRQ_NOREQUEST);
 
        /* We use the level handler only for now, we might want to
         * be more cautious here but that works for now
         */
-       irq_to_desc(virq)->status |= IRQ_LEVEL;
+       irq_set_status_flags(virq, IRQ_LEVEL);
        set_irq_chip_and_handler(virq, &i8259_pic, handle_level_irq);
        return 0;
 }
 
 {
        int level1;
 
-       irq_to_desc(virq)->status |= IRQ_LEVEL;
+       irq_set_status_flags(virq, IRQ_LEVEL);
 
        level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
        BUG_ON(level1 > MV64x60_LEVEL1_GPP);
 
        chip = &qe_ic->hc_irq;
 
        set_irq_chip_data(virq, qe_ic);
-       irq_to_desc(virq)->status |= IRQ_LEVEL;
+       irq_set_status_flags(virq, IRQ_LEVEL);
 
        set_irq_chip_and_handler(virq, chip, handle_level_irq);
 
 
        DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
        if ((virq >= 1) && (virq <= 4)){
                irq = virq + IRQ_PCI_INTAD_BASE - 1;
-               irq_to_desc(irq)->status |= IRQ_LEVEL;
+               irq_set_status_flags(irq, IRQ_LEVEL);
                set_irq_chip(irq, &tsi108_pci_irq);
        }
        return 0;
 
 
 uic_irq_ret:
        raw_spin_lock(&desc->lock);
-       if (desc->status & IRQ_LEVEL)
+       if (irqd_is_level_type(&desc->irq_data))
                chip->irq_ack(&desc->irq_data);
-       if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
+       if (!(irq_is_disabled(&desc->irq_data) && chip->irq_unmask)
                chip->irq_unmask(&desc->irq_data);
        raw_spin_unlock(&desc->lock);
 }