PCI: imx6: Factor out PHY reset

Split the PCIe PHY reset from the link up function to make the code a
little more structured.

No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Frank Li <lznuaa@gmail.com>
Cc: Harro Haan <hrhaan@gmail.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Sean Cross <xobs@kosagi.com>
Cc: Siva Reddy Kallam <siva.kallam@samsung.com>
Cc: Srikanth T Shivanand <ts.srikanth@samsung.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Yinghai Lu <yinghai@kernel.org>

diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index 5634a33ea6421fdbf7324fb9856df01aa70c79c1..25dde2c7b445a5a6b85e61da931b988d97ee32c6 100644 (file)
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -336,9 +336,26 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
        return;
 }
 
+static void imx6_pcie_reset_phy(struct pcie_port *pp)
+{
+       uint32_t temp;
+
+       pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
+       temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
+                PHY_RX_OVRD_IN_LO_RX_PLL_EN);
+       pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
+
+       usleep_range(2000, 3000);
+
+       pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
+       temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
+                 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
+       pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
+}
+
 static int imx6_pcie_link_up(struct pcie_port *pp)
 {
-       u32 rc, ltssm, rx_valid, temp;
+       u32 rc, ltssm, rx_valid;
 
        /*
         * Test if the PHY reports that the link is up and also that
@@ -370,21 +387,7 @@ static int imx6_pcie_link_up(struct pcie_port *pp)
 
        dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n");
 
-       pcie_phy_read(pp->dbi_base,
-               PHY_RX_OVRD_IN_LO, &temp);
-       temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
-               | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
-       pcie_phy_write(pp->dbi_base,
-               PHY_RX_OVRD_IN_LO, temp);
-
-       usleep_range(2000, 3000);
-
-       pcie_phy_read(pp->dbi_base,
-               PHY_RX_OVRD_IN_LO, &temp);
-       temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
-               | PHY_RX_OVRD_IN_LO_RX_PLL_EN);
-       pcie_phy_write(pp->dbi_base,
-               PHY_RX_OVRD_IN_LO, temp);
+       imx6_pcie_reset_phy(pp);
 
        return 0;
 }