net: stmmac: dwmac-qcom-ethqos: Fix drops in 10M SGMII RX

In 10M SGMII mode all the packets are being dropped due to wrong Rx clock.
SGMII 10MBPS mode needs RX clock divider programmed to avoid drops in Rx.
Update configure SGMII function with Rx clk divider programming.

Fixes: 463120c31c58 ("net: stmmac: dwmac-qcom-ethqos: add support for SGMII")
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Signed-off-by: Sneh Shah <quic_snehshah@quicinc.com>
Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20231212092208.22393-1-quic_snehshah@quicinc.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index d3bf42d0fceb69bd084b9d05db0f7dacdb8cff18..31631e3f89d0a499f04b26ed79b159e99cea4879 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -34,6 +34,7 @@
 #define RGMII_CONFIG_LOOPBACK_EN               BIT(2)
 #define RGMII_CONFIG_PROG_SWAP                 BIT(1)
 #define RGMII_CONFIG_DDR_MODE                  BIT(0)
+#define RGMII_CONFIG_SGMII_CLK_DVDR            GENMASK(18, 10)
 
 /* SDCC_HC_REG_DLL_CONFIG fields */
 #define SDCC_DLL_CONFIG_DLL_RST                        BIT(30)
@@ -78,6 +79,8 @@
 #define ETHQOS_MAC_CTRL_SPEED_MODE             BIT(14)
 #define ETHQOS_MAC_CTRL_PORT_SEL               BIT(15)
 
+#define SGMII_10M_RX_CLK_DVDR                  0x31
+
 struct ethqos_emac_por {
        unsigned int offset;
        unsigned int value;
@@ -598,6 +601,9 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos)
        return 0;
 }
 
+/* On interface toggle MAC registers gets reset.
+ * Configure MAC block for SGMII on ethernet phy link up
+ */
 static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
 {
        int val;
@@ -617,6 +623,10 @@ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
        case SPEED_10:
                val |= ETHQOS_MAC_CTRL_PORT_SEL;
                val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
+               rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR,
+                             FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR,
+                                        SGMII_10M_RX_CLK_DVDR),
+                             RGMII_IO_MACRO_CONFIG);
                break;
        }